Broadcom Corporation

Texas Instruments Corporation

Kang Xiao

Chung-Jue Chen

Hongtao Jiang

Zhongfeng Wang

Dennis Keats

Jun Cao

Afshin Momtaz

Sudeep Bhoja

Mario Caresosa

Steve Thomas

Robert Holder

Timothy Chan

James R Fife

Ali Ghiasi

Namik Kocaman

Vivek Telang

Andrew Yanowitz

Xin Wang

Jay Proano

David Chung

Joanne Wu

Randall Stolaruk

Dong Cho

Vikram Natarajan

Randy Stolaruk

Stephen Finch

Patrick Conley

Mark J Blair

James Schaffner

Natarajan Vikram

Aspects of a method and system for encoding in 100G-KR networking are described. In one example embodiment, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block, and encoding a data stream including the transcoded block.

Method and system for encoding for 100G-KR networking

A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider.

Multi-channel multi-protocol transceiver with independent channel configuration using single frequency reference clock source

Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such (e.g., possibly by performing bit-flipping), various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.

Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein

Electronic dispersion compensation within optical communications using reconstruction. Within a communication system that includes any optical network portion, segment, or communication link, etc., that optical component/portion of the communication system is emulated within the electronic domain. For example, in a communication device having receiver functionality, deficiencies that may be incurred by the at least one optical portion of the communication system are compensated in the electronic domain of the communication device having the receiver functionality by employing reconstruction logic and/or circuitry therein. Multiple decision feedback equalizers (DFE) circuitries, implemented in the electronic domain, may be employed to provide feedback from different portions of the receiver functionality in accordance with performing compensation of optical incurred deficiencies (e.g., dispersion, non-linearity, inter-symbol interference (ISI), etc.). Within a communication device's receiver portion, equalization and compensation is performed in the electronic domain as adapted for high speed applications and higher order modulation schemes.

Electronic dispersion compensation within optical communications using reconstruction

Various examples are provided for encoding for 100G-KR networking. In one example, among others, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block and encoding a data stream including the transcoded block.

Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.

Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits. In addition, interleaving may be performing at various stages of the encoding processing.

Forward error correction (FEC) scheme for communications

A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal.

System and method for generating two effective frequencies using a single clock

A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceiver chip through at least a part of an out-bound data path of the transceiver chip, is detected, then a more reliable secondary clock signal is substituted for the primary clock signal. Once it is determined that the primary clock signal has recovered, the primary clock signal is switched back to and certain discrete circuits of the out-bound data path of the transceiver chip are automatically reset in hardware without the need for system level intervention to avoid any problems due to clock glitches on the primary clock signal during the switching.

System and method supporting auto-recovery in a transceiver system

Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Transceiver system and method supporting variable rates and multiple protocols

A method of implementing a geometry per wedge (GPW) based headerless solution in a disk drive formatter having a corresponding memory buffer. The disk drive formatter includes high and low processing engines and formats a data storage disk. The method includes the step of processing a command instruction, which instructs the high-level processing engine to execute a disk operation with respect to a predetermined sector. The method also includes the steps of searching for the predetermined sector using sector layout information derived from a GPW table including entries which define the relative position of sector pulses on a track within a data wedge of the disk, and transferring the predetermined sector from the disk to the buffer memory.

Method of implementing a geometry per wedge (GPW) based headerless solution in a disk drive formatter and a computer program product incorporating the same

An apparatus is employed for providing for efficient communication between high level and low level processing engines in a disk formatter for formatting a disk, the high-level engine outputting at least one instruction to control disk operations to the low-level engine which processes the instruction. The apparatus includes an instruction queue within the low-level engine. The instruction queue stores the instruction received by the low level processing engine from the high level processing engine, which outputs the instruction to the memory in accordance with a first clock signal generated by the high-level engine. The instruction queue outputs the instruction in accordance with a second clock signal of the low level processing engine which corresponds to a predetermined disk transfer rate. In accordance with another embodiment of the present invention, a method is also employed for providing for efficient communication between high and low level processing engines in a disk formatter for formatting a disk. The method includes the steps of storing an instruction for controlling disk operations output by the high level processing engine in an instruction queue of the low-level engine. The instruction is output by the high level processing engine in accordance with a first clock signal of the high level processing engine. In addition, the instruction is output from the instruction queue in accordance with a second clock signal of the low level processing engine which corresponds to a predetermined disk transfer rate.

Apparatus and method for providing for efficient communication between high and low-level processing engine of a disk drive formatter

A programmable disk formatter for a disk controller in a headerless hard disk drive (HDD) system is disclosed. The disk formatter includes a high level processing engine that generates on the fly low level instructions that are executed by a low level processing engine. The disk formatter also includes a servo interface for interfacing the disk formatter to the servo timing logic, sector direct memory access (SDMA), and a QT/SP interface for interfacing the disk formatter to other processors in the disk controller, such as a system processor (SP) or Q-transmogrifier (QT) processor. The high level engine and low level engine operate semi-independently. The former processes SP- or QT-converted host computer commands in such a fashion that the low level instructions are generated and passed by the high level engine in time for the low level engine to execute them in coordination with the disk data rate. The high level engine is programmable with a high level instruction set, assembly language in the preferred embodiment, so that different drive formats can be accommodated with only software changes involving reprogramming of the high level engine and certain tracking/geometry tables stored in memory. The architecture and logic of the disk controller render a highly flexible, easily programmable. user friendly solution to the problem that disk controller designers face in accommodating each new generation of magnetic disks and each new approach to formatting.

Programmable high performance disk formatter for headerless disk drive

The present invention provides a method and apparatus for providing position detection using a unique binary sequence encoded in indexing bits stored in servo wedges. The present invention generates a unique binary sequence (UBS) code and stores the bits of such a code in the indexing bits of the servo wedges. The bits are read from the servo wedges and used to provide unique identification of head position. Each servo wedge and each data field can be uniquely identified, even servo wedges and data fields under different heads. The present invention may be used to provide initial position detection, position verification during normal operation, and position verification upon head switching. When used for position verification, the present invention uses a confidence block to determine the confidence level with which the head is believed to be correctly positioned. One or more programmable thresholds may be used to qualify operations such as reading information from a disk, writing information to a disk, or seeking a location on a disk. If these thresholds are not met for the corresponding operations, the initial position detection capability of the present invention may be used to provide position recovery.

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Irvine, CA, United States of America

Kang Xiao