Samsung Electronics Co., Ltd.

Kang-Wook Lee

Gu-Sung Kim

Keum-Hee Ma

Dong-Hyeon Jang

Young-Hee Song

Se-Young Jeong

Yong-Chai Kwon

Ki-Tae Park

Seung-Duk Baek

Se-Yong Oh

Jae-Sik Chung

Seong-Il Han

Ho-jin Lee

Hyun-Kyoung Kim

Suk-Chae Kang

Young-Don Choi

Nam-seog Kim

Yun-sang Lee

Son-Kwan Hwang

Myeong-Soon Park

Soon-Bum Kim

Sung-min Sim

Ju-il Choi

Jin-Hak Choi

Ung-Kwang Kim

Dong-Ho Lee

Ju-Il Choi

Sun-Won Kang

Mitsuo Umemoto

Dong-ho Lee

Jong-woo Kim

Son-kwan Hwang

Myung-Kee Chung

Myeong-soon Park

Yong Chai Kwon

Sun-Wook Heo

Seong-II Han

Jung-Hang Yi

Seong-il Han

A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Stacked semiconductor apparatus, system and method of fabrication

Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Integrated circuit chips having vertically extended through-substrate vias therein

A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region.

Semiconductor device having through electrode and method of fabricating the same

Methods of forming integrated circuit chips having vertically extended through-substrate vias therein

A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Chipstack package and manufacturing method thereof

A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.

Wafer level stack structure for system-in-package and method thereof

Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.

Stack module, card including the stack module, and system including the stack module

Methods of forming integrated circuit chips having vertically extended through-substrate vias therein and chips formed thereby

A method of forming a wafer level stack structure, including forming a first wafer including a first device chip, wherein the first device chip includes a plurality of input/output (I/O) pads, forming a second wafer including a second device chip, wherein each second device chip contains a second plurality of I/O pads, the second device chip is approximately equal in size to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including a first device chip having a first plurality of input/output (I/O) pads and a second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.

Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.

Semiconductor structure and method for forming the same

Growing community of inventors

Suwon-si, South Korea

Kang-Wook Lee