Magnachip Semiconductor, Inc.

Sk Keyfoundry Inc.

Key Foundry Co., Ltd

Kang Sup Shin

Jong Yeul Jeong

Yang Beom Kang

Hee Baeg An

Kwan Soo Kim

Jeong Ho Sheen

Francois Hebert

Dong Joon Kim

Young Joon Kim

Seong Min Choe

Seong Woo Lee

Sang Geun Koo

Seung Han Ryu

Kyung Soo Kim

Kyung Ho Lee

Tae Jong Lee

Si Bum Kim

Guk Hyeon Yu

A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

Semiconductor device having high breakdown voltage capacitor

A method for manufacturing a semiconductor device is provided. The method includes providing a high-voltage isolation capacitor region and a mixed-signal integrated circuit region on a substrate, forming a bottom electrode on the high-voltage isolation capacitor region, forming a bottom metal line on the mixed-signal integrated circuit region, forming an inter-metal dielectric layer on the bottom electrode and the bottom metal line, forming a top via in the inter-metal dielectric layer, forming a low bandgap dielectric layer on the top via and the inter-metal dielectric layer, patterning the low bandgap dielectric layer to form a patterned low bandgap dielectric layer, depositing a thick metal film on the top via and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top metal line on the high-voltage isolation capacitor region and form a top electrode on the mixed-signal integrated circuit region.

Semiconductor device and semiconductor device manufacturing method with high-voltage isolation capacitor

A semiconductor device includes a substrate, the substrate includes a capacitor region and a metal wiring region. The capacitor region includes a lower electrode formed on the substrate, an interlayer insulating layer formed on the lower electrode, a dielectric layer pattern formed on the interlayer insulating layer, and an upper electrode formed on the dielectric layer pattern. The metal wiring region includes a lower metal wiring formed parallel to the lower electrode, the interlayer insulating layer formed on the lower metal wiring, an upper insulating layer formed on the interlayer insulating layer and having a thickness smaller than a thickness of the interlayer insulating layer, and an upper metal wiring formed on the upper insulating layer, and formed in parallel with the upper electrode. The upper insulating layer and the dielectric layer pattern are formed of different materials.

Semiconductor device having a high breakdown voltage capacitor and method for forming the same

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

Semiconductor device having deep trench structure and method of manufacturing thereof

A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing area comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.

Semiconductor device having circuitry positioned above a buried magnetic sensor

A semiconductor device includes a semiconductor region, deep trenches, a dielectric film, a conductive material, an interlayer insulating film, and a metal interconnection. The semiconductor region has a first conductivity type in a silicon substrate. The deep trenches are disposed in the semiconductor region. The dielectric film is disposed on sidewalls of the deep trenches. The conductive material is disposed on the dielectric film. The interlayer insulating film is disposed on upper surface portions of the deep trenches to create a void inside each of the deep trenches. The metal interconnection is disposed on the interlayer insulating film.

Semiconductor device having a deep-trench capacitor including void and fabricating method thereof

Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.

Magnetic sensor and method of fabricating the same

A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing are comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.

A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.

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Cheongju-si, South Korea

Kang Sup Shin