Skhynix Inc.

Kang Sub Kwak

Yoo Jong Lee

Sang Sic Yoon

Young Jun Yoon

A semiconductor device includes a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation, configured to generate a pull-down driving signal that is enabled when any one of a write signal and a read signal is input, and configured to generate the pull-down driving signal that is enabled after a set interval when a synchronization signal is input, and a sync enable signal generation circuit configured to generate a sync enable signal for receiving a data clock from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.

Semiconductor system

A semiconductor device includes a phase control signal generation circuit, a phase detection circuit, and a selection/transmission circuit. The phase control signal generation circuit outputs one of a command-shifted signal generated from a command/address signal and a clock-shifted signal generated from a clock signal as a phase control signal, based on a leveling enablement signal. The phase detection circuit detects a phase of a leveling clock signal in synchronization with the phase control signal to generate a detection signal. The selection/transmission circuit outputs the detection signal as one of a phase detection signal and a phase adjustment signal based on the leveling enablement signal.

Semiconductor devices and semiconductor systems

A semiconductor device includes a phase difference detection circuit and an internal circuit. The phase difference detection circuit generates first and second phase difference detection signals by comparing a phase of a phase detection clock signal, generated from a command/address signal in synchronization with a clock signal, with phases of a division clock signal and an internal division clock signal that are generated by dividing a frequency of a data clock signal according to an operation mode. The internal circuit recognizes the phases of the division clock signal and the internal division clock signal according to a logic level combination of the first and second phase difference detection signals.

Semiconductor devices for recognizing a phase of a division clock signal

A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.

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Seoul, South Korea

Kang Sub Kwak