Skhynix Inc.

Industry-University Cooperation Foundation Hanyang University

Hynix Semiconductor Inc.

Kang-Sub Kwak

Young-Jun Yoon

Oh-Kyong Kwon

Yong-Ju Kim

Hae-Rang Choi

Joon-Yong Choi

Jun-Yong Song

Hyeon-Cheon Seol

Sang-Sic Yoon

Ki-Up Kim

Jong-Hyun Ra

A semiconductor memory device includes a memory region from which first data and second data are sequentially read, and a data output circuit suitable for selectively performing a reset operation on a data pad according to a logical relationship between the first and second data during an output disable period between a first output enable period corresponding to first output data and a second output enable period corresponding to second output data, when sequentially outputting the first and second output data corresponding to the first and second data through the data pad.

Cryogenic transmitter and semiconductor memory device including the same

A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Memory system and operating method thereof

A semiconductor device includes a transmission circuit coupled between a first voltage supply node and a second voltage supply node, and suitable for outputting an output data signal corresponding to a data value to an output terminal during a data output enable period, and a switching circuit coupled between the first and second voltage supply nodes, and suitable for providing a current path between the first and second voltage supply nodes during a data output disable period.

Cryogenic transmitter

A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a DED parity corrector suitable for correcting any error of the second sub-parity based on the second sub-parity error flag.

Memory system and operating method of the memory system

An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.

Semiconductor memory device for resetting counter synchronized with data clock by using reset signal synchronized with system clock and method for operating the same

A data transmitter may include a transmitter circuit and a calibration controller. The transmitter circuit is configured to be coupled to a receiver through a channel, and configured to provide an output signal to the channel based on an input signal and adjust an output impedance value according to a bias signal. The calibration controller is configured to adjust the bias signal by comparing the output signal of the transmitter circuit to a reference signal during a calibration operation.

Data transmitter

A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

Majority decision circuit

A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

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Seoul, South Korea

Kang-Sub Kwak