Skhynix Inc.

Hynix Semiconductor Inc.

Kang Sik Choi

Jang Uk Lee

Suk Ki Kim

Sung Cheoul Kim

Sang Min Kim

Sang Yong Lee

Jung Ryul Ahn

Sang Hyun Oh

Seung Bum Cha

Nam Kyun Park

Jin Ha Kim

Young Ho Lee

Seung Cheol Lee

Su Jin Chae

Bong Hoon Lee

Jun Kwan Kim

Sung Lae Oh

Hae Chan Park

Sang Hyun Sung

Dong Yean Oh

Ja Chun Ku

Jin Hyock Kim

Hyun Soo Shin

Jung Won Seo

Joo Hyung Bae

A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.

Three-dimensional semiconductor device

A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.

Semiconductor memory device and manufacturing method of the semiconductor memory device

Provided herein may be a semiconductor device. The semiconductor device may include a first stacked body including a first stacked insulating layer and a first stacked conductive layer that are alternately stacked; a capacitor plug passing through the first stacked body; and a capacitor multi-layered layer configured to enclose the capacitor plug. The capacitor plug may include metal.

Semiconductor device and method of manufacturing the semiconductor device

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.

Semiconductor device and manufacturing method of the semiconductor device

A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.

Semiconductor device and manufacturing method of semiconductor device

A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming a first opening that passes through the stack, forming a blocking layer in the first opening, forming a data storage layer in the blocking layer, forming a slit passing through the stack, forming second openings by selectively removing the second material layers through the slit, selectively forming a protective layer on exposed surfaces of the first material layers, etching the blocking layer through the second openings, oxidizing the protective layer, and forming insulating layers in the second openings.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.

A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

Semiconductor device and manufacturing method thereof

The disclosure relates to a highly integrated memory device and a method for manufacturing the same. According to the disclosure, a memory device comprises a lower structure, an active layer horizontally oriented parallel to a surface of the lower structure, a bit line connected to a first end of the active layer and vertically oriented from the surface of the lower structure, a capacitor connected to a second end of the active layer, a word line horizontally oriented to be parallel with the active layer along a side surface of the active layer, and a fin channel layer horizontally extending from one side surface of the active layer, wherein the word line includes a protrusion covering the fin channel layer.

Growing community of inventors

Gyeonggi-do, South Korea

Kang Sik Choi