Samsung Display Co., Ltd.

Samsung Displayco., Ltd.

Kang Moon Jo

Dong Woo Kim

Jun Hyun Park

An Su Lee

Sung Jae Moon

Young Wan Seo

Chong Chul Chai

Il Gon Kim

Se Hyoung Cho

Kyung-Hoon Kim

Young Joo Choi

Joon Geol Kim

Seung-Ho Jung

Bo Yong Chung

Woo Geun Lee

Woo-Seok Jeon

Woong-Sik Choi

Sho Yeon Kim

Chong Chui Chai

Byung Hwan Chu

Young Min Kim

Kyung Hoon Kim

Cheol-Gon Lee

Hui-Won Yang

Tae-Young Choi

Bo Sung Kim

Tak-Young Lee

June Whan Choi

Yang Hwa Choi

Seung Ho Jung

Jee Hoon Kim

Tak-young Lee

Jong Moo Huh

Seon-Pil Jang

Woong Sik Choi

Yeon Taek Jeong

Yong Duck Son

Ki Beom Lee

Jae Seol Cho

A display device including: a substrate including a display area and a non-display area; a light-emitting element disposed in the display area; an encapsulation layer covering the light-emitting element; a driving unit disposed in the non-display area; a dam surrounding the display area and overlapping the driving unit, and a shielding layer overlapping the driving unit.

Display device

An organic light emitting diode display includes a clock wiring circuit including a first signal line and a second signal line, a resistance adjusting circuit including a first lower resistance line and a first upper resistance line connected to the first signal line and a second lower resistance line and a second upper resistance line connected to the second signal line, and a gate driving circuit connected to the resistance adjusting circuit. The second signal line is disposed closer to the gate driving circuit than the first signal line, the first lower resistance line and the second lower resistance line have higher resistivity than the first upper resistance line and the second upper resistance line, respectively, the first lower resistance line is shorter than the second lower resistance line, and the first upper resistance line is longer than the second upper resistance line.

Organic light emitting diode display

A display device includes a substrate including a display area and a non-display area around the display area; a transistor on the substrate; an insulating layer on the transistor; a power voltage line on the insulating layer and transferring a power voltage; a data line on the insulating layer and transferring a data voltage; and an auxiliary wire between the substrate and the power voltage line in the display area. The auxiliary wire includes a portion overlapping the power voltage line and a portion overlapping the data line in a plan view and is electrically connected to the power voltage line.

A scan signal driving unit capable of reducing the RC delay of scan control lines in an ultra-high resolution display, such as 8K UHD. The scan signal driving unit includes a plurality of stages configured to sequentially output scan signals, first clock lines to which first clock signals are applied, and second clock lines to which second clock signals are applied. Each of the first clock lines includes a (1-1)-th metal pattern and a (1-2)-th metal pattern disposed on the (1-1)-th metal pattern. Each of the second clock lines includes a (2-1)-th metal pattern disposed on the same layer as one of the (1-1)-th metal pattern and the (1-2)-th metal pattern.

Scan signal driving unit and display device including the same

A display device includes a substrate including a display area and a non-display area; a semiconductor layer including a source area, a channel area, and a drain area and disposed in the non-display area of the substrate; a gate electrode overlapping the channel area of the semiconductor layer; a gate insulating layer disposed between the gate electrode and the channel area of the semiconductor layer; a source electrode electrically connected to the source area of the semiconductor layer; and a drain electrode electrically connected to the drain area of the semiconductor layer, wherein a lateral side of the gate electrode overlaps the drain electrode.

Display device with a static electricity discharging circuit

The present disclosure relates to a display device, and the display device according to an exemplary embodiment of the present inventive concept includes: a first pixel circuit portion including at least one transistor; a second pixel circuit portion including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion; a first data line electrically connected to the first pixel circuit portion; and a second data line electrically connected to the second pixel circuit portion, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel electrode overlaps the first data line and the second data line in a plan view.

Display device with reduced parasitic capacitances between pixel electrodes and data lines

A display device includes a first pixel including a first transistor, a second transistor, and a third transistor, a second pixel disposed adjacent to the first pixel in a first direction, and including a first transistor, a second transistor, and a third transistor, and an initialization voltage line disposed between the first pixel and the second pixel, and extending in a second direction crossing the first direction. The second transistor of the first pixel and the second transistor of the second pixel are connected to the initialization voltage line. The first, second, and third transistors of the first pixel and the first, second, and third transistors of the second pixel are symmetrical with respect to the initialization voltage line.

Display device including a first capacitor with a gate electrode and a second capacitor with a data line

There are provided a gate driver and a display device including the same. The gate driver includes: a first scan driver; a first sensing driver; a first scan clock line; and a first sensing clock line. The first scan clock line includes a first scan clock main line extending in one direction, and a first scan clock connection line connected to the first scan clock main line and the first scan driver. The first sensing clock line includes a first sensing clock main line extending in one direction, and a first sensing clock connection line connected to the first sensing clock main line and the first sensing driver. The first scan clock main line is closer to each of the first scan driver and the first sensing driver than the first sensing clock main line.

Gate driver and display device including the same

A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

A display device includes a first conductive layer, a first insulation layer disposed on the first conductive layer, and active patterns disposed on the first insulation layer. The display device further includes a second conductive layer disposed on the active patterns and including a first gate electrode that overlaps a channel region of the active patterns and a driving gate electrode, a second insulation layer disposed on the second conductive layer, a third conductive layer including a capacitor electrode and at least one scan line disposed on the second insulation layer, a third insulation layer disposed on the third conductive layer, and an electrode layer including a first electrode disposed on the third insulation layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

A display device includes: a substrate; a first conductive layer including a lower pattern disposed on the substrate; an active layer including a first active pattern disposed on the first conductive layer; and a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps a first channel region included in the first active pattern, the lower pattern overlaps the first active pattern, and the first active pattern does not cross an edge of the lower pattern.

Display device having a lower pattern overlapping an active pattern

A display device including: a substrate; first, second, and third data lines extending in a first direction on the substrate and disposed to be adjacent along a second direction crossing the first direction; a semiconductor layer disposed on the first, second, and third data lines; a first insulating layer disposed on the semiconductor layer; first, second, and third lower storage electrodes disposed on the first insulating layer and arranged to be adjacent along the first direction; a second insulating layer disposed on the first, second, and third lower storage electrodes; a first scan line extending in the second direction on the second insulating layer; a first pixel connected to the first scan line and the first data line; a second pixel connected to the first scan line and the second data line; and a third pixel connected to the first scan line and the third data line.

An organic light emitting diode display includes a substrate, a semiconductor pattern disposed on the substrate, a first conductive layer disposed on the semiconductor pattern and including a first gate electrode having an island-shaped structure, a second gate electrode having an island-shaped structure, and a third gate electrode having an island-shaped structure, and a second conductive layer disposed on the first conductive layer and including a first initialization voltage line overlapping the first gate electrode, a scan line overlapping the second gate electrode, and a control signal line overlapping the third gate electrode, where the control signal line is electrically connected to the third gate electrode, the scan line is electrically connected to the second gate electrode, and the first initialization voltage line, the scan line, and the control signal line extend in a first direction.

Organic light emitting diode display having electrode structure for improved display quality

An organic light emitting diode display including: a data wiring that includes a main data line disposed in a display area and a first data line disposed in a peripheral area; a driving voltage wiring that includes a main driving voltage line disposed in the display area and a first driving voltage line that is connected with the main driving voltage line and disposed in the peripheral area while extending in a first direction; and a driving low-voltage wiring that includes a cathode extending to the peripheral area while overlapping the display area, and a plurality of first driving low-voltage connection portions that are connected with the cathode and disposed in the peripheral area, wherein each of the plurality of first driving low-voltage connection portions comprises a wiring portion extended in the first direction and a pad portion electrically connected with the wiring portion.

Growing community of inventors

Hwaseong-si, South Korea

Kang Moon Jo