University of California

General Electric Company

National Applied Research Laboratories

Kang-Lung Wang

Ji-Young Kim

Chih-Kong Ken Yang

Gregory Paul Carman

Dejan Markovic

Pedram Khalili Amiri

Augustin Jinwoo Hong

Wen-Kuan Yeh

Guoqiang Yu

Fengbo Ren

Roland K Kawakami

Qiming Shao

Yi Zhou

Robert F Reihl

Wei Han

Tao Wu

Alexandre Bur

Ajey Poovannummoottil

Yann-Wen Lan

Faxian Xiu

The present invention relates to an inductive spin-orbit torque device and the method for fabricating the same. The method comprises steps of depositing a two-dimensional thin film using chemical vapor deposition (CVD) and sputtering a ferromagnetic material on the thin film. The crystal structure of the two-dimensional thin film includes at least one lattice plane arranged asymmetrically. The thickness of the two-dimensional thin film includes at least one unit-cell layer. The sum of the at least one unit-cell layer is an odd number. By using the vertical magnetic torque generated by the two-dimensional thin film and the miniaturization in thickness, the device size and the fabrication costs may be reduced.

Inductive spin-orbit torque device and method for fabricating the same

A ferroelectric device includes a first electrode, a second electrode spaced apart from the first electrode, and a ferroelectric element arranged between the first and second electrodes. The ferroelectric element has a plurality of quasistatic strain configurations that are selectable by the application of an electric field and the device has selectable electromechanical displacement by the application of the electric field.

Tunable and metastable ferroelectric materials and magneto-electric devices

As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1 V supply voltage, which is greater than reference designs achieve at 5 ns performance.

Body voltage sensing based short pulse reading circuit

A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO(BFO). As a result, the multiferroic material layer enables an electrically modulated magnetic exchange bias that enhances paramagnetic to ferromagnetic switching of the DMS channel. The DMS channel is formed of a DMS material, which in one embodiment is Manganese Germanium (MnGe). In one embodiment, the DMS channel is a nanoscale DMS channel.

Spin transistor having multiferroic gate dielectric

A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers.

All graphene flash memory device

The embodiments disclosed herein relate to growth of magnesium-oxide on a single crystalline substrate of germanium. The embodiments further describes a method of manufacturing and crystalline structure of a FM/MgO/Ge(001) heterostructure. The embodiments further related to method of manufacturing and a crystalline structure for a high-k dielectric//MgO [100](001)//Ge[110](001) heterostructure.

Epitaxial growth of single crystalline MgO on germanium

A low resistance electrical contact is made to a silicon substrate by forming a layer of a refractory metal on the substrate and thereafter applying a dosage of ions through the layer of refractory metal to the substrate to form a layer of a compound of the refractory metal and silicon at the interface of the layer of refractory metal and the silicon substrate.

Method of making low resistance contacts in semiconductor devices by ion

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Santa Monica, CA, United States of America

Kang-Lung Wang