University of California

Samsung Electronics Co., Ltd.

Basf Se Corporation

Intel Corporation

USA As Represented by Secretary of the Navy

The State University of New York

University of Nebraska

Inston, Inc.

Mastek International

Kang L Wang

Pedram Khalili Amiri

Alexander Khitun

Kosmas Galatsis

Ji-Young Kim

Jeong-Hee Han

Augustin Jinwoo Hong

Yong-Jik Park

Bo Wang

Omar M Yaghi

Dejan Markovic

William Thomas Lynch

Hiroyasu Furukawa

Alexander U Czaja

Mary M Eshaghian-Wilner

Fei Liu

Juan G Alzate

Timothy K Carns

Xinyu Zheng

Martin O Tanner

Richard Dorrance

Dmitri E Nikonov

Mau-Chung Frank Chang

Peter A Dowben

Ryan P Lu

Hochul Lee

Tatsuo Itoh

Mildred S Dresselhaus

Theodore C Harman

James R Adleman

Qi Hu

Jonathan Bird

Tomislav Suligoj

Christian Binek

Carlos M Torres, Jr

Stephen B Cronin

Jin S Park

Jianlin Liu

Filipp A Baron

Takaaki Koga

Xiangzhong Sun

Guoqiang Yu

Yaohui Zhang

Yongxi Qian

Igor V Roshchin

Xia Hong

Ma Siguang

Hao-Yuan Chang

Roman P Ostroumov

Petar Biljanovic

Zhongming Zeng

Perng-Fei Yuh

Pramey Upadhyaya

Jason C Woo

Mingqiang Bao

Antiferromagnetic magneto-electric spin-orbit read (AFSOR) logic devices are presented. The devices include a voltage-controlled magnetoelectric (ME) layer that switches polarization in response to an electric field from the applied voltage and a narrow channel conductor of a spin-orbit coupling (SOC) material on the ME layer. One or more sources and one or more drains, each optionally formed of ferromagnetic material, are provided on the SOC material.

Magneto-electric logic devices using semiconductor channel with large spin-orbit coupling

Systems and methods in accordance with embodiments of the invention implement select devices constructed from 2D materials. In one embodiment, a crossbar memory system includes: a first set of connection lines; a second set of connection lines; and an array of memory cells, each memory cell including: a select device; and a memory device; where each memory cell is coupled to a unique combination of: at least one connection line from the first set of connection lines, and at least one connection line from the second set of connection lines; and where at least one select device includes a 2D material.

Systems and methods for implementing select devices constructed from 2D materials

A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.

Self-organized critical CMOS circuits and methods for computation and information processing

A device includes a substrate with a tunnel barrier disposed on active region defined on the substrate, a monolayer of graphene disposed on the tunnel barrier, a dielectric material disposed on the graphene, and an electrode disposed over a region of the dielectric material. A first voltage is applied across the electrode and the graphene to adjust a Fermi level within the graphene to a Fermi level position within the valence band of the graphene based upon a predetermined emission wavelength. A current is injected into the graphene's conduction band to cause the graphene to emit a broadband hot electron luminescence (HEL) spectrum of photons peaked at the predetermined emission wavelength. The device may be configured as a vertical-tunneling light-emitting hot-electron transistor. The broadband HEL photon emission spectrum emanating from the graphene may be voltage-tunable within the electromagnetic spectrum from UV to THz.

Tunable graphene light-emitting device

A fast and low-power sense amplifier and writing circuit for high-speed Magnetic RAM (MRAM) which provides the long retention times and endurance of magnetic tunnel junction (MTJ) cells, while providing faster access speeds, verified writes, and an increased sensing margin. A high-speed and low-power pre-read and write sense amplifier (PWSA) provide VCMA effect precessional switching of MTJ cells which include pre-read and comparison steps which reduce power consumption. An embodiment of the PWSA circuit is described with write and pre-charge circuit, S and D latches, comparison circuit, and a differential amplifier and control circuit.

Fast and low-power sense amplifier and writing circuit for high-speed MRAM

A nanoscale tunnel magneto-resistance (TMR) sensor comprising an in-plane-magnetized reference layer and a free layer comprising interfacial perpendicular anisotropy, wherein the free layer comprises a sensing layer for sensing resistance as a function of applied magnetic field and is tunable to vary the direction of the sensing layer magnetization to be in-plane, canted, or out-of-plane.

Magnetoresistance sensor with perpendicular anisotropy

Embodiments of the technology implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between said fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series.

DIOMEJ cell device

Embodiments of the technology implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between the fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series.

Systems and methods for implementing magnetoelectric junctions

Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at high cell densities. Implementations are described which provide a wide range of voltage control alternatives with in-plane and perpendicular magnetization, bidirectionally switched magnetization, and control of domain wall dynamics.

Voltage-controlled magnetic anisotropy (VCMA) switch and magneto-electric memory (MERAM)

A basic Spin-Orbit-Torque (SOT) structure with lateral structural asymmetry is provided that produces a new spin-orbit torque, resulting in zero-field current-induced switching of perpendicular magnetization. More complex structures can also be produced incorporating the basic structure of a ferromagnetic layer with a heavy non-magnetic metal layer having strong spin-orbit coupling on one side, and an insulator layer on the other side with a structural mirror asymmetry along the in-plane direction. The lateral structural asymmetry and new spin-orbit torque, in effect, replaces the role of the external in-plane magnetic field. The direction of switching is determined by the combination of the direction of applied current and the direction of symmetry breaking in the device.

Magnetic memory bits with perpendicular magnetization switched by current-induced spin-orbit torques

A frequency conversion device, which may include a radiofrequency (RF) mixer device, includes a substrate and a ferromagnetic film disposed over a surface of the substrate. An insulator is disposed over the ferromagnetic film and at least one microstrip antenna is disposed over the insulator. The ferromagnetic film provides a non-linear response to the frequency conversion device. The frequency conversion device may be used for signal mixing and amplification. The frequency conversion device may also be used in data encryption applications.

Frequency mixer having ferromagnetic film

Voltage-controlled magnetic anisotropy (VCMA) switch and magneto-electric memory (MeRAM)

Embodiments of the invention implement MEJs having improved read-write characteristics. In one embodiment, an MEJ includes: ferromagnetic fixed and free layers, a dielectric layer interposed between the ferromagnetic layers, and an additional dielectric layer proximate the free layer, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when subject to a potential difference, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, compared to the strength of the magnetic anisotropy along the first easy axis, is magnified during the application of the potential difference, where the extent of the magnification is enhanced by the presence of the additional layer.

Systems and methods for implementing magnetoelectric junctions having improved read-write characteristics

An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same

Growing community of inventors

Santa Monica, CA, United States of America

Kang L Wang