Samsung Electronics Co., Ltd.

International Business Machines Corporation

Kang Ill Seo

Joon Goo Hong

Yong Hee Park

Borna Josip Obradovic

Sa Hwan Hong

Myung Gil Kang

Byounghak Hong

Seunghyun Song

Hwichan Jun

Inchan Hwang

Young Chai Jung

Tae Yong Kwon

Seon Bae Kim

Oh Seong Kwon

Ki Sik Choi

Integrated circuit devices and methods of forming the same are provided. The methods may include sequentially forming an underlying mask layer and a preliminary first mask layer on a substrate, forming a first mask structure by removing a portion of the preliminary first mask layer, and then forming a preliminary second mask layer. The preliminary second mask layer may enclose the first mask structure in a plan view. The methods may also include forming a second mask structure by removing a portion of the preliminary second mask layer and forming a vertical channel region including a portion of the substrate by sequentially etching the underlying mask layer and the substrate. The second mask structure may be connected to the first mask structure, and etching the underlying mask layer may be performed using the first and the second mask structures as an etch mask.

Integrated circuit devices including an element having a non-linear shaped upper surface and methods of forming the same

Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

Vertical field-effect transistor (VFET) devices and methods of forming the same

A semiconductor device include: a substrate; a 1transistor formed above the substrate, the 1transistor including a 1channel set of a plurality of 1nanosheet layers, a 1gate structure surrounding the 1nanosheet layers, and 1and 2source/drain regions at both ends of the 1channel set; and a 2transistor formed above the 1transistor in a vertical direction, the 2transistor including a 2channel set of a plurality of 2nanosheet layers, a 2gate structure surrounding the 2nanosheet layers, and 3and 4source/drain regions at both ends of the 2channel set, wherein the 1channel set has a greater width than the 2channel set, wherein a number of the 1nanosheet layers is smaller than a number of the 2nanosheet layers, and wherein a sum of effective channel widths of the 1nanosheet layers is substantially equal to a sum of effective channel width of the 2nanosheet layers.

Semiconductor device having stepped multi-stack transistor structure

Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.

VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.

Vertical FET devices including a contact on protruding portions of a substrate

A method for providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed by the mask. The method also performs an anneal in a volume-increasing ambient, such as hydrogen, at anneal temperature(s) above one hundred degrees Celsius and not more than six hundred degrees Celsius. The second portion of each of the fins is exposed during the anneal such that the second portion of each of the fins undergoes a volume expansion.

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Eumseong-gun, South Korea

Kang Ill Seo