Samsung Electronics Co., Ltd.

Kang Hun Moon

Choeun Lee

Yang Xu

Sujin Jung

Jinbum Kim

Jin Bum Kim

Seokhoon Kim

Byeongchan Lee

Namkyu Cho

Sihyung Lee

Kwan Heum Lee

Hyun-Kwan Yu

Sanggil Lee

Chul Kyu Kim

Dong Woo Kim

Kyung Ho Kim

Hyo Jin Kim

Ki Hwan Kim

Sun Jung Kim

Dong Suk Shin

Kyung Yub Jeon

Kyungho Kim

Cho Eun Lee

Bon Young Koo

Haegeon Jung

Jeong Ho Yoo

Do Hee Kim

Il Gyou Shin

Si Hyung Lee

Jae Myung Choe

Yonguk Jeon

A semiconductor device is provided. The semiconductor device includes: an active pattern extending in on a substrate; nanosheets stacked on the active pattern; a gate electrode on the active pattern and surrounding the nanosheets; a source/drain trench on the active pattern adjacent the gate electrode; and a source/drain region in the source/drain trench, The source/drain region includes: a first layer provided along a sidewall and a bottom surface of the source/drain trench, the first layer having a first n-type impurity doped therein; a second layer on the first layer in the source/drain trench, the second layer having germanium (Ge) doped therein; and a third layer filling a remaining portion of the source/drain trench on the second layer, the third layer having a second n-type impurity doped therein.

Semiconductor device

A semiconductor device includes a substrate including an active pattern; a source/drain pattern on the active pattern; a gate electrode on the active pattern; and a gate spacer on the source/drain pattern. The source/drain pattern includes a first semiconductor layer on the active pattern and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes a first inner sidewall and second inner sidewall on the second semiconductor layer. A distance between the first and second inner sidewalls of the first semiconductor layer decreases according as positions of two portions of the first semiconductor layer where the distance is measured become closer to the gate spacer decreases.

Semiconductor device and method of fabricating the same

Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

A semiconductor device includes a plurality of active fins on a substrate, a gate electrode intersecting the plurality of active fins, and a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode. The source/drain region includes lower epitaxial layers on ones of the plurality of active fins. The lower epitaxial layers include germanium (Ge) having a first concentration. An upper epitaxial layer is on the lower epitaxial layers, and includes germanium (Ge) having a second concentration that is higher than the first concentration. The lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.

Semiconductor devices

A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

Semiconductor devices and methods of fabricating the same

A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

Method of fabricating semiconductor device

Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

Semiconductor devices and methods of manufacturing the same

A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a 'U'-shaped section; and forming source/drain regions in the recess regions.

A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.

Semiconductor device having contact plugs

Growing community of inventors

Incheon, South Korea

Kang Hun Moon