Electronics and Telecommunications Research Institute

Sangyung University Industry-Academy Cooperation Foundation

Kang Ho Kim

Hyun Soo Kim

Kwang Ryong Oh

Kwang-Won Koh

Jong Hoi Kim

Oh Kee Kwon

Kwang Won Koh

Changdae Kim

Taehoon Kim

Eun Deok Sim

Sung In Jung

Soo Cheol Oh

Seung Hyub Jeon

Myung Lae Lee

Soo Young Kim

Yong Soon Baek

Jung Ho Song

Jin Mee Kim

Jeong Hwan Lee

Yeon Jeong Jeong

Chei Yol Kim

Eun Ji Lim

Seung-Chul Lee

Chang Won Ahn

Seungjo Bae

Seung Jun Cha

Je Man Lee

Ki-Hyuk Nam

Dong Ha Shin

Sungik Jun

Disclosed is a method of managing a disaggregated memory. According to the present disclosure, the method includes: assigning at least one memory page to a local memory and a remote memory; checking a request for access to the memory page; checking whether a target performance ratio required in service is satisfied or not when the memory page requested to be accessed is assigned to the remote memory; predicting a size of the local memory on the basis of an LRU distance-based histogram when the target performance ratio is not satisfied; and reassigning the memory page requested to be accessed in consideration of the predicted size of the local memory.

Apparatus for managing disaggregated memory and method thereof

Disclosed is a quantum diagnostic circuit, which includes an input unit having an input of at least first to fourth qubits, a diagnostic circuit unit receiving the first to fourth qubits from the input unit and providing a quantum superposition and a quantum entanglement, and an output unit receiving an output of the diagnostic circuit unit and determining whether the output is in a Bell-state, and the diagnostic circuit unit includes a Hadamard gate processing the first qubit to provide the quantum superposition of the first to fourth qubits, a first CNOT gate providing the quantum entanglement between an output of the Hadamard gate and the second qubit, a second CNOT gate providing the quantum entanglement between an output of the first CNOT gate and the third qubit, and a third CNOT gate providing the quantum entanglement between an output of the second CNOT gate and the fourth qubit.

Quantum diagnostic circuit and quantum characteristic diagnostic method

A memory access method and device are provided. A memory access method may include: identifying, when an access to a page of a remote memory occurs, a type of the access; allocating a sparse buffer when the access is a sparse write; storing data for the sparse write in the sparse buffer; storing an address for the sparse write as a key and the sparse buffer as a value in a buffer table; and updating an instruction pointer to point to a next instruction.

Method and device for accessing memory

An apparatus for memory integrated management in a cluster system including a plurality of physical nodes connected to each other by a network determines one of the plurality of physical nodes as a node to place a new virtual machine, allocates the first type of memory allocated to the one physical node to the new virtual machine as much as the memory capacity required by the new virtual machine, and distributes the second type of memory to a plurality of virtual machines running on the plurality of physical nodes by integrating and managing the second type of memory allocated to each of the plurality of physical nodes. In this case, the access speed of the second type of memory is faster than that of the first type of memory.

Method and apparatus for memory integrated management of cluster system

An apparatus for genome sequence alignment attempts a search for the hash tables to align a target nucleotide sequence, from a hash table having a large seed size to a hash table having a small seed size, and when there is at least one matched seed to the target nucleotide sequence on a hash table, aligns the target nucleotide sequence by using candidate positions from the hash table without further hash table searching.

Method for genome sequence alignment and apparatus thereof

According to a method of transforming a message passing interface (MPI) program, an MPI function is parsed such that a computer may directly access data created by another computer through a memory when an MPI parallel program is executed on a computer system for distributed processing, a network function corresponding to the MPI function is created for network communication, and a bus line function is created for directly accessing the memory through a bus line.

Method and apparatus for transformation of MPI programs for memory centric computers

The preset specification provides a method of managing a disaggregated memory in a virtual system. Herein, the disaggregated memory managing method includes: detecting a memory access pattern in a virtual machine node based on an operation of a virtual machine; and performing a memory operation by using a memory block in consideration of the memory access pattern, wherein the memory access pattern is variably set based on a time at which the operation of the virtual machine is performed, and the memory block dynamically changes in size based on the memory access pattern.

Method and apparatus for managing disaggregated memory

Scheduling threads in a system with many cores includes generating a thread map where a connection relationship between a plurality of threads is represented by a frequency of inter-process communication (IPC) between threads, generating a core map where a connection relationship between a plurality of cores is represented by a hop between cores, and respectively allocating the plurality of threads to the plurality of cores defined by the core map, based on a thread allocation policy defining a mapping rule between the thread map and the core map.

Method for scheduling threads in a many-core system based on a mapping rule between the thread map and core map

A method for memory management, include allocating an empty page of a physical memory for reference data according to execution of an application program, and mapping the empty page to a virtual memory; checking a physical address of the physical memory to which the reference data has been loaded; mapping the checked physical address to the virtual memory to which the empty page has been mapped, and mapping the reference data; and releasing allocation of the allocated physical memory when the reference data is mapped to the virtual memory.

Method and apparatus for memory management

An OS switching method for switching an OS within several seconds in an information processing system is provided. In the information processing system which includes a processor, a main memory, a nonvolatile memory, and a plurality of input/output apparatuses, an OS switcher is executed when power is applied to the information processing system. When a first OS acquires an OS switch command that indicates a switch to a second OS while the first OS is activated and running, the first OS stores identification information of the second OS and information indicating an OS switch in the nonvolatile memory, and performs STR. The OS switcher switches an OS from the first OS to the second OS after the STR is completed. Accordingly, in the system, one OS can be quickly switched to another OS within several seconds, and a previous working environment can be maintained.

Operating system switching method in information processing system including a switcher checking wakeup status in the processor

A virtualization apparatus includes: an emulation manager for searching a basic block cache for an entry with an entry point, and, if there exists no entry with the entry point in the basic block cache, requesting the identification of a basic block corresponding to the entry point; a basic block identifier for identifying the basic block by sequentially analyzing instructions of a source binary in response to a request from the emulation manager; and an instruction replacer for writing an entry of the identified basic block in a replaced instruction table, writing a branch instruction for the entry of the basic block in the source binary, and then branching to the entry point. The apparatus further includes an instruction emulator for executing an instruction of the basic block when a branch to the entry point is made.

Virtualization apparatus and processing method thereof

A data transfer apparatus, system and method using the same are provided. A data transfer system according to an exemplary embodiment includes a user process space, a kernel space and a hardware space. A plurality of user processes are executed in the user process space. The kernel space includes a kernel thread. The hardware space performs an input/output according to the input/output request of the each user process. When input data based on the input request are received to the hardware space, the data transfer system checks whether the user process requesting the input is in an execution state, and allows the kernel thread to copy the input data from the kernel space to the user process space when the user process is in the execution state.

Data transfer apparatus, system and method using the same

A method for switching a communication channel in a shared memory communication environment which sets up a TCP/IP (Transmission Control Protocol/Internet Protocol) communication channel and a shared memory communication channel from a first virtual machine to a second virtual machine, the method includes: transmitting a channel switching message to the first virtual machine when the first virtual machine moves to another physical machine; transmitting the channel switching message from the first virtual machine to the second virtual machine; and switching a channel state between the first virtual machine and the second virtual machine.

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Daejeon, South Korea

Kang Ho Kim