Sony Corporation

Sony Semiconductor Solutions Corporation

Kaneyoshi Takeshita

Akihiro Nakamura

Kazuki Nomoto

Hiroyuki Ohri

Takashi Kubodera

Takeshi Matsushita

Junya Suzuki

Toshiharu Yanagida

Fumio Nagumo

Masaharu Hamasaki

Takeo Hashimoto

Masayuki Miyabayashi

Yukihiro Kiyota

A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.

Solid-state imaging device

There is provided a solid-state image sensor including a plurality of unit pixels arranged thereon, the plurality of unit pixels each including a light receiving section which stores a charge generated by photoelectric conversion, a signal storage section which is connected to the light receiving section and has a structure of a MOS capacitor, and a signal output section to which a gate electrode of the MOS capacitor is connected.

Solid-state image sensor with MOS capacitor storage section to which a negative bias is applied after a reset sampling period and electronic device incorporating same

Disclosed herein is a solid-state imaging element including: (A) a light reception/charge storage region formed in a semiconductor layer, the light reception/charge storage region including M light reception/charge storage layers stacked one on top of the other, where M&#x2267;2; (B) a charge output region formed in the semiconductor layer; (C) a conduction/non-conduction control region which includes a portion of the semiconductor layer located between the light reception/charge storage region and the charge output region; and (D) a conduction/non-conduction control electrode adapted to control the conduction or non-conduction state of the conduction/non-conduction control region, wherein mth potential control electrodes are provided between the mth and (m+1)th light reception/charge storage layers, where 1&#x2266;m&#x2266;(M&#x2212;1), to control the potentials of the light reception/charge storage layers.

Solid-state imaging element and driving method of the solid-state imaging element

An imaging apparatus includes: an imaging unit configured to image an image using an imaging device; an image obtaining unit configured to obtain a plurality of images equivalent to the time of dark, imaged by the imaging unit; a registering unit configured to register, with an image obtained by the image obtaining unit, the address and change amount of a pixel where the output value of the pixel changes so as to exceed a predetermined threshold; and a correcting unit configured to correct, when taking a pixel corresponding to an address registered by the registering unit as a processing object pixel, the pixel value of the processing object pixel based on comparison between difference of the output values of the processing object pixel and a peripheral pixel of the processing object pixel, and the change amount of the processing object pixel.

Imaging apparatus and method, electronic device, and program

A solid-state image pickup element includes: (A) a light receiving/charge accumulating region formed in a semiconductor layer and formed by laminating M (where M&#x2267;2) light receiving/charge accumulating layers; (B) a charge outputting region formed in the semiconductor layer; (C) a depletion layer forming region formed of a part of the semiconductor layer, the part of the semiconductor layer being situated between the light receiving/charge accumulating region and the charge outputting region; and (D) a control electrode region for controlling a state of formation of a depletion layer in the depletion layer forming region, wherein the solid-state image pickup element further includes a light receiving/charge accumulating layer extending section extending from each light receiving/charge accumulating layer to the depletion layer forming region.

Solid-state image pickup element and driving method thereof

A semiconductor device is characterized by mixedly mount a logic chip, an analog chip, a memory chip, etc. by stacking them while stabilizing power supply lines and ground lines of each chip. The semiconductor device has an intermediate substrate having a conductive portion and also having, on its one surface, an external connection terminal conducted to the conductive portion; and semiconductor chips each of which has connection portions, and which are mounted on both the surfaces of the intermediate substrate. At least two of the above semiconductor chips are electrically conducted to each other via the conductive portion of the intermediate substrate. At least one of a power supply line, a ground line, and a signal line of each of the semiconductor chips is connected to the conductive portion of the intermediate substrate via two or more, conducted to each other, of the connection portions.

Semiconductor device

A charge-coupled device including a semiconductor substrate of given conductivity type, a buried channel formed on the substrate of different conductivity type than the substrate, an electrically floating diffusion formed in the substrate of different conductivity type than the substrate, and a plurality of electrodes insulating from the buried channel. The electrodes are responsive to applied voltages for supplying a signal charge through the buried channel to the floating diffusion. The charged-coupled device also includes a transistor responsive to a pulse voltage signal for periodically resetting the floating diffusion to a predetermined potential. The transistor comprises an enhancement type surface channel field effect transistor.

Charge-coupled device floating diffusion output reset

A semiconductor memory device having a number of memory cells. Each of the memory cells comprises a diode having a first electrode connected to a bit line. The diode has a second electrode connected at a point to one terminal of a storage capacitor, the other terminal of which is connected to a word line. A reset circuit is provided for resetting the point to a predetermined potential.

Semiconductor memory device using diode-capacitor combination

A folded line DRAM having shared sense amplifiers wherein one of two the memory cell arrays is provided with a pair of switches for dividing the bit line pairs into plural bit line pair groups and the second memory cell array is provided with separate switches connected in series the bit line pairs for the purpose of reducing power consumption caused by charging and discharging of the bit lines during accessing.

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Tokyo, Japan

Kaneyoshi Takeshita