Fujitsu Corporation

Kaneyasu Shimoda

Tadayoshi Katoh

Yuzo Ageno

Hideto Furukawa

Atsushi Yamashita

This invention provides a demodulation method and a demodulator for demodulating by converting analog signal obtained by reading information stored in a recording medium to digital signal so as to generate data representing that information. Consequently, correct data is obtained from signal having low S/N ratio. Over-sampling is carried out by an A/D converter A and a digital signal synchronous with a proper clock is reproduced by interpolation computation, maximum likelihood is detected and RLL decoded. Then, error is corrected by an error correction code.

Demodulation method and demodulator

&ldquo;100&rdquo;, which is one of the (1, 7) RLL codes, is used as a clock acquisition pattern. After temporarily judging the sample output to be one of (1, &minus;1), the phase error computing result for three samples (symbols) is added so as to cancel the errors of phase computing. Therefore the number of judgment states can be decreased, and phase can be acquired at high-speed even if the amplitude at acquisition has not been defined. At tracking, the sample output is judged to be one of three groups, &lsqb;1&plus;a, 1&rsqb;, 0, and &lsqb;&minus;1, &minus;1&minus;a&rsqb;. Using the state transition of (1, 7) RLL codes, &lsqb;1&plus;a, 1&rsqb; and &lsqb;&minus;1, &minus;1&minus;a&rsqb; are distinguished. Since the number of judgment states decreases, judgment accuracy improves.

Phase synchronization method for extended partial response, and phase synchronization circuit and read channel circuit using this method

An encoding unit includes a separating section for separating a RLL code into a restricting portion corresponding to a basic code and a non-restricting portion corresponding to information bits, a first encoding section for adding an error correction code to the restricting portion and carrying out a RLL encoding, a second encoding section for adding an error correction code to the non-restricting portion, and an interleaving section for interleaving outputs of the first and second encoding means, and outputting encoded information.

Encoding unit and decoding unit

In a signal processing apparatus according to the present invention employing PRML technology to reproduce a code sequence recorded on a magnetic recording medium, the maximum likelihood code sequence of a readback signal is obtained by using a likelihood function based on a conditional distribution of each branch corresponding to a quantization level. A plurality of conditional distributions having various deviations are provided, and a suitable conditional distribution is selected in accordance with the characteristic of the readback signal, the signal reproduction performance can be improved. Especially set is a conditional distribution for the nonlinear phenomenon, such as the nonlinear transition shift (NLTS) and the partial erasure (PE). Therefore, it is possible to prevent the signal processing performance deterioration, caused by the nonlinear phenomenon, which tends to appear more often in consonance with the increase in the recording density of a magnetic recording medium. In addition, the recording density for a magnetic recording medium can be increased.

Signal processing apparatus and signal processing method

A recording unit converts input data into a (1, 7) RLL code by a (1, 7) RLL encoder to record it onto a medium. A reproducing unit equalizes a regenerative signal from the medium by use of a transfer function (1+D) (1+1.5D+D.sup.2) of an equalizer 44. After the limitation to a narrow band up to a spectrum null by a lowpass filter, the reproducing unit detects data by a maximum likelihood detector and decodes original data from (1, 7) RLL code data by means of a (1, 7) RLL decoder.

Record reproduction apparatus

A maximum likelihood detection method detects a maximum likelihood path using trellis transitions when decoding a code string which is obtained by encoded data by a sliding block coding employing trellis-coded partial response (TCPR) technique. The maximum likelihood detection method includes the steps of (a) inputting the code string, and (b) detecting a maximum likelihood path with respect to the code string from state transition paths using a number of trellis transition states greater than a number of states of a state transition pattern of the sliding block code.

Maximum likelihood detection method and information recording and

A maximum likelihood detection of a convolution code Yn obtained by coupling a transversal equalizer to a code Zn of a recording and reproducing channel. A branch metric is arithmetically operated by changing a weight of a data train of a convolution code corresponding to multiplication coefficients of a filter by a distributor with respect to a reproduction signal Rn. On the basis of the branch metric, an ACS circuit judges a maximum likelihood path at every path node and the results are stored into a path memory 56. Simultaneously with the maximum likelihood detection, metrics of the maximum likelihood paths judged with respect to the path nodes are compared by a maximum likelihood path comparing circuit, thereby deciding the maximum likelihood path node. A maximum inclination arithmetic operating circuit calculates a maximum inclination of the multiplication coefficients of the filter. The next multiplication coefficients are updated by an updating circuit.

Information reproducing apparatus and its automatic equalization maximum

Disclosed are an encoding method and demodulating method for a PRML system for maximum-likelihood-detecting and demodulating a encoded partial response signal. The encoding method comprises a step of segmenting an input data string into 4-bit data and a step of converting the 4-bit data into 6-bet code words Y={001011, 001101, 001110, 010011, 010110, 011001, 011010, 011100, 100011, 100101, 100110, 101001, 101100, 110001, 110010, 110100}. The demodulating method includes a maximum likelihood detection step by use of a trellis transition, said trellis transition includes path transitions between status A groups {001A, 010A, 100A, 011A, 101A, 110A} constituting last-half 3 bits of the 6-bit code word and status B groups {001B, 010B, 100B, 011B, 101B, 110B} constituting first-half 3 bits of the 6-bit code word and path transitions from the status B groups to the status A groups including path transitions from 011B, 101B, 110B to 001A, 010A, 100A excluding the path transition from 101B to 010A and path transitions from 001B, 010B, 100B to 011A, 101A, 110A excluding the path transition from 010B to 101A.

Encoding method for PRML system, method of and apparatus for

In a magnetic disk drive for writing write data by a head to a magnetic disk, equalizing a reproduced signal read out from the magnetic disk by a head at the time of reproduction, and effecting maximum likelihood detection for the reproduced signal after equalization and thus demodulating the read data, '1s' are periodically inserted as dummy bits into a data string of the write data. On the other hand, a timing signal and a clock signal which are synchronous with the positions of the dummy bits are generated from the reproduced signals after equalization, and a threshold level of binary/ternary judgement is switched by this timing signal. Binary judgement is made at the position of the dummy bit in the reproduced signal after equalization and path merge is unconditionally regarded as existing at the position of the dummy bit in the reproduced signal after equalization, and path retrieval is made, while ternary judgement is made for other code strings to execute maximum likelihood detection. As a result, in a magnetic disk drive for demodulating the read data by the maximum likelihood detection method, error propagation can be reduced, the encoding gain can be improved and a high speed maximum likelihood detection can be accomplished.

Magnetic disk drive in which read data is demodulated using maximum

In a clock generator for magnetic disk drive of the zone-bit recording type in which a training signal is written in a preamble portion of data, comprising: a sample-holder circuit for generating a sampling signal from a read signal; a phase-comparator for detecting a phase difference from the sampling signal; a loop filter; and a voltage-controlled oscillator whose frequency is controlled by the phase difference as it is smoothed; there is provided a frequency divider; a clock extraction circuit for extracting a clock timing from the training signal as it is equalized partially-response signal; and a phase-comparator for finding a phase difference from an output of the frequency divider and an output of the clock extraction circuit, and the phase-comparator is connected to the loop filter during reproduction of the preamble portion of the data and the phase-comparator is connected to the loop filter during reproduction of a data portion of the data by the switching of a change-over switch. As a result, hangup is prevented and an accurate clock timing in the clock generator.

Clock generator for magnetic disk drive that switches between preamble

In a phase synchronization circuit for generating a clock signal from an input signal, having a VCO, a phase comparator for comparing the phase of the input signal with that of an output signal of the VCO, and a loop filter for receiving an output signal of the phase comparator and providing a control voltage for the VCO, the loop filter includes first and second voltage-current converters for receiving the output signal of the phase comparator; a capacitor to be charged and discharged according to an output current of the first voltage-current converter; and a resistor for converting the output signal of the second voltage-current converter into the control voltage for the VCO. The ratio between currents for the input and output stages of a current multiplier in each of the first and second voltage-current converters is changed according to a control current provided through a control terminal when the frequency of the input signal is changed, to thereby change a transconductance of the converters without changing a damping factor. In this way, the circuit speedily carries out phase synchronization without changing a damping factor even if the frequency of an input signal is changed.

Phase synchronization circuit having a loop filter including two

A viterbi equalizer includes a distributor for receiving a run length limited code and for calculating branch metrics responsive to the run length limited code. The branch metrics are related to only nodes and branches in a trellis state transition diagram based on a viterbi decoding algorithm defined for the run length limited code. The viterbi equalizer also includes a path metric calculating circuit, operatively coupled to the distributor, for generating path metrics on the basis of the branch metrics and for generating path select signals indicative of surviving paths coupling the nodes and branches. Further, the viterbi equalizer includes a path memory, operatively coupled to the path metric calculating circuit, for determining a maximum likelihood path on the basis of the path select signals output by the path metric calculating circuit.

Viterbi equalizer and recording/reproducing device using the same

A sequential decoder for decoding a systematic and convolutional code signal having a code rate greater than 1/2 and carrying out error correction coding of the code signal. A local most likely path in a plurality of possible paths for a newly received information bit is determined by calculating a branch metric indicating likelihood of each of the plurality of possible paths in accordance with a predetermined algorithm. The path decision is carried out by a construction including a two-path comparing path decision circuit which receives a pair of bits comprised of an information bit and a parity bit at one time and determining a local most likely path between two possible paths for the information bit. A four-path comparing path decision circuit receives a pair of information bits at one time and determines a local most likely path among four possible paths for the pair of information bits. A parity bit timing detecting circuit detects a timing of an input of the above pair of bits comprised of an information bit and a parity bit. A selecting circuit selects an output of the above two-path comparing path decision circuit at the input timing of the above pair of bits comprised of an information bit and a parity bit, and selects an output of the above four-path comparing path decision circuit at the timing of the input of the above pair of information bits.

Sequential decoder

An integrated viterbi decoder structure and method, the viterbi decoder receives test input signals at a distributor, an ACS circuit and a path memory and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder.

Viterbi decoder and method for testing the viterbi decoder

A sequential decoding device for decoding a data expressed by a systematic code having a symbol memory, a maximum likelihood path decision circuit, and a path memory, includes: an overflow detection circuit for detecting an overflow of the symbol memory, and a switch for supplying signal bit data, as an decoded output, read from the symbol memory directly to the path memory in correspondence with an overflow detection signal from the overflow detection circuit. The device includes further a path metric value increase/decrease monitoring circuit for monitoring the increase/decrease of a path metric value delivered from the maximum likelihood path decision circuit and controlling the switch in such a manner that, when a monotonous increase of path metric value is detected, the decoded output of the maximum likelihood path decision circuit is supplied to the path memory instead of a direct supply of the decoded output of the symbol memory to the path memory.

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Kawasaki, Japan

Kaneyasu Shimoda