Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Other

Texas Instruments Corporation

Hiachi, Ltd.

Kanehide Kenmizaki

Masaya Muranaka

Yukihide Suzuki

Makoto Morino

Tetsuya Kitame

Shinichi Miyatake

Masahiro Ogata

Katsuyuki Sato

Michitaro Kanamitsu

Nobuo Kato

Takeshi Kajimoto

Kiichi Manita

Yutaka Shimbo

Shouji Kubono

Shunichi Sukegawa

Tsugio Takahashi

Shoji Kubono

Masayuki Nakamura

Sinichi Miyatake

Katsuo Komatsuzaki

Shoji Wada

Makoto Saeki

Hiromi Matsuura

Yoshihisa Koyama

Hidetomo Aoyagi

Masahiro Katayama

Nobuhiko Ohno

Chisa Makimura

Seiichi Shundo

Osamu Okayama

Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

Semiconductor memory device and memory system

A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.

Dynamic RAM

A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.

Semiconductor memory system

The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal. Such availability of plural self-refresh modes becomes particularly advantageous when considering consumption of the back-up power for maintaining the IC memory device versus stability of stored data. While the consumption of the back-up power for maintaining the device would be relatively lower under one of the self-refresh modes, namely, the PS (pseudo) refresh mode, the stability of data stored would, however, be greater under another self-refresh mode, namely, the VS (virtual) refresh mode.

Semiconductor memory device facilitated with plural self-refresh modes

There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input terminal, and a test mode can be effected in which the refresh period can be set at an optional value by accordingly applying a test control signal to a predetermined external terminal. Therefore, the discharge current of the oscillation circuit capacitor associated with the refresh timer circuit becomes stabilized, noting the particular layout arrangement regarding the polycrystalline silicon layer forming the resistor of the oscillation circuit, and the fact that same parasitic capacitances are effectively connected between the polycrystalline silicon resistor and the supply voltage of the circuit and between the polycrystalline silicon resistor and the ground potential of the circuit thereby cancelling any variation of the output of the power source. Therefore, variation of the oscillation frequency of the oscillation circuit attributable to the bumping of the power source can be effectively suppressed.

Semiconductor memory, components and layout arrangements thereof, and

A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.

Data output buffer for a semiconductor memory

A semiconductor memory having a memory array, a first and a second selection line which are connected to a memory cell, and a selection means which selects either one of the selection lines. The selection means includes a selection circuit which optionally selects the first selection line or the second selection line when an address signal corresponding to the first selection line is aligned with a predetermined address signal.

Semiconductor memorizing device

Growing community of inventors

Kodaira, Japan

Kanehide Kenmizaki