Tokyo Electron Limited

Tokyo Electron Limi Ted

Toyko Electron Limited

Kandabara N Tapily

Jeffrey Smith

Robert Daniel Clark

Anton J deVillers

Gerrit J Leusink

Lars W Liebmann

Kai-Hung Yu

Subhadeep Kal

Cory Wajda

Daniel Chanemougame

David L O'Meara

Takahiro Hakamata

Angelique Denise Raley

Nihar Mohanty

Nicholas Joy

Hiroaki Niimi

Jodi Grzeskowiak

Gyanaranjan Pattanaik

Takaaki Tsunomura

Mark I Gardner

Takashi Ando

H Jim Fulford

Vijay Narayanan

Eduard Albert Cartier

Paul Charles Jamison

Qiang Zhao

Kaoru Maekawa

Richard Farrell

Genji Nakamura

Soo Doo Chae

Marinus J P Hopstaken

Steven Consiglio

Hirokazu Aizawa

Sophie Thibaut

Jason Mehigan

Tadahiro Ishizaka

Akiteru Ko

Kaushik Arun Kumar

Andrew W Metz

Takashi Matsumoto

Aelan Mosden

Yun Han

Hoyoung Kang

Yusaku Kashiwagi

Shan Hu

Yusuke Yoshida

Henan Zhang

Xinghua Sun

Paul Gutwin

Takeshi Itatani

Satoru Nakamura

Ying Trickett

Fumitaka Amano

Wanjae Park

Sangcheol Han

Hisashi Higuchi

Karthikeyan Pillai

Chihiro Tamura

Hiroki Niimi

Robert Clark

Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.

Thermal etching of ruthenium

A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.

Method of conductive material deposition

Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

Self-aligned method for vertical recess for 3D device integration

A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.

Dual metal wrap-around contacts for semiconductor devices

A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.

Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks

In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.

Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory

A substrate processing method for area selective deposition includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film. In one example, the first film contains a metal film, second film contains a metal-containing liner that surrounds the metal film, and the third film includes a dielectric film that surrounds the metal-containing liner.

Method for mitigating lateral film growth in area selective deposition

A substrate processing method includes (a) providing a substrate in a substrate processing tool, the substrate containing an exposed surface of a first material layer and an exposed surface of a second material layer; (b) forming a self-assembled monolayer (SAM) on the substrate in a first substrate processing chamber (SPC); (c) transferring the substrate from the first SPC through a substrate transfer chamber to a second SPC; (d) depositing a film selectively on the first material layer and film nuclei on the SAM in the second SPC; (e) transferring, after selectively depositing the film on the first material layer, the substrate from the second SPC through the substrate transfer chamber to a third SPC; (f) removing the film nuclei from the SAM by etching in the third SPC; and repeating (b), (c), (d), (e) and (f) sequentially at least once.

Substrate processing tool with integrated metrology and method of using

A semiconductor device includes conductive structures formed in a first dielectric layer, a conductive cap layer selectively positioned over the conductive structures and the first dielectric layer with a top surface and sidewalls, a second dielectric layer selectively positioned over the first dielectric layer and disposed between the sidewalls of the conductive cap layer, a third dielectric layer selectively positioned over the second dielectric layer and disposed between the sidewalls of the conductive cap layer, a fourth dielectric layer arranged over the conductive structures and the third dielectric layer, and an interconnect structure formed in the fourth dielectric layer. The interconnect structure includes a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure. The via structure includes a first portion positioned over the conductive cap layer and a second portion disposed over the first portion and the third dielectric layer.

Fully self-aligned via with selective bilayer dielectric regrowth

A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing Hgas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

Method for controlling the forming voltage in resistive random access memory devices

In method for forming a semiconductor device, a first opening is formed in a dielectric stack that has a cylinder shape with a first sidewall. A first conductive layer is deposited along the first sidewall of the first opening and a first insulating layer is deposited along an inner sidewall of the first conductive layer. The dielectric stack is then etched along an inner sidewall of the first insulating layer so as to form a second opening that extends into the dielectric stack with a second sidewall. A second conductive layer is further formed along the second sidewall of the second opening and a second insulating layer is formed along an inner sidewall of the second conductive layer. A bottom of the second conductive layer is positioned below a bottom of the first conductive layer to form a staggered configuration.

Coaxial contacts for 3D logic and memory

A substrate processing method includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film by vapor deposition. In one example, the first film, second film, and the third film are selected from the group consisting of a metal film, a metal-containing liner, and a dielectric film.

Method for reducing lateral film formation in area selective deposition

Methods are provided for selective film deposition. One method includes providing a substrate containing a dielectric material and a metal layer, the metal layer having an oxidized metal layer thereon, coating the substrate with a metal-containing catalyst layer, treating the substrate with an alcohol solution that removes the oxidized metal layer from the metal layer along with the metal-containing catalyst layer on the oxidized metal layer, and exposing the substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiOfilm on the metal-containing catalyst layer on the dielectric material.

Method of selective deposition for forming fully self-aligned vias

A method of fabricating air gaps in advanced semiconductor devices for low capacitance interconnects. The method includes exposing a substrate to a gas pulse sequence to deposit a material that forms an air gap between raised features.

Method of forming a semiconductor device with air gaps for low capacitance interconnects

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Growing community of inventors

Albany, NY, United States of America

Kandabara N Tapily