Fujitsu Corporation

Kanae Nakagawa

Masataka Mizukoshi

Kazuaki Kurihara

Takeshi Shioga

John David Baniecki

Taiji Sakai

Kazuo Teshirogi

Yoshikatsu Ishizuki

Takashi Suzuki

Masaki Arai

Yasumoto Tomita

Motoaki Tani

Keishiro Okamoto

Nawalage Florence Cooray

A barrier synchronization circuit that performs barrier synchronization of a plurality of processes executed in parallel by a plurality of processing circuits, the barrier synchronization circuit includes a first determination circuit configured to determine whether the number of first processing circuits among the plurality of the processing circuits is equal to or greater than a first threshold value, the first processing circuits having completed the process, and an instruction circuit configured to instruct a second processing circuit among the plurality of the processing circuits to forcibly stop the process when it is determined that the number is equal to or greater than the first threshold value by the first determination circuit, the second processing circuit having not completed the process.

Barrier synchronization circuit, barrier synchronization method, and parallel information processing apparatus

A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization. The parallel information processing apparatus includes: a completion information storage configured to store completion information, wherein the completion information includes information relating to completion of processing of an own apparatus and information relating to completion of processing of a lower information processing apparatus located in the tree structure; and a control circuit configured to, in response to a determination result indicating that a current status amounts to a given condition, instruct a specified information processing apparatus to forcibly suspend processing, the specified information processing apparatus being an apparatus that has not yet completed processing before all of the plurality of information processing apparatuses have completed the processing.

Barrier synchronization system and parallel information processing apparatus

A thermoelectric conversion module includes a thermoelectric conversion element, a container, a heat storage material accommodated in the container, and a first heat transfer member thermally coupled to one side of the thermoelectric conversion element and thermally coupled to the heat storage material, wherein the first heat transfer member includes a portion made of a solid-solid phase transition system heat storage material having a thermal conductivity higher than a thermal conductivity of the heat storage material and having a transition temperature different from a transition temperature of the heat storage material.

Thermoelectric conversion module, sensor module, and information processing system

A heat dissipating component comprising: a main body formed from a first material; a heat dissipating sheet that is formed from a second material having higher thermal conductivity than the first material, that is provided at the main body, and that includes a plurality of fins thermally connected to each other at positions other than apexes and a connecting portion thermally connecting the plurality of fins to an electronic component; and a covering portion that covers at least a portion of a bottom portion of a groove between the plurality of fins.

Heat dissipating  component, manufacturing method for heat dissipating component, electronic device, manufacturing method for electronic device, integrated module, and information processing system

A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.

Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus

A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.

Method for manufacturing interposer

The resin layer formation method comprises the step of forming on a substratea resin layerfor containing a substance for decreasing the thermal expansion coefficient to thereby forming a resin layerhaving said substance localized in the side thereof nearer to the substrate; and the step of cutting the surface of the resin layerwith a cutting toolto planarize the surface of the resin layer. The resin layeras said substance for decreasing the thermal expansion coefficient localized in the side thereof nearer to the substrate, and the surface of the resin layeris cut to planarize the surface of the resin layer, whereby the extreme abrasion and breakage of the cutting toolby said substance for decreasing the thermal expansion coefficient can be prevented.

Resin layer formation method and semiconductor device fabrication method

The plating method comprises the step of forming a resin layerover a substrate; the step of cutting the surface part of the resin layerwith a cutting tool; the step of forming a seed layeron the resin layerby electroless plating; and the step of forming a plating filmon the seed layerby electroplating. Suitable roughness can be give to the surface of the resin layer, whereby the adhesion between the seed layerand the resin layercan be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layeras are by desmearing treatment, whereby a micronized pattern of a photoresist filmcan be formed on the resin layer. Thus, interconnections, etc. can be formed over the resin layerat a narrow pitch with high reliability ensured.

Plating method, semiconductor device fabrication method and circuit board fabrication method

The plating method comprises the step of forming a resin layerover a substrate; the step of cutting the surface part of the resin layerwith a cutting tool; the step of forming a seed layeron the resin layerby electroless plating; and the step of forming a plating filmon the seed layerby electroplating. Suitable roughness can be give to the surface of the resin layer, whereby the adhesion between the seed layerand the resin layercan be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer, as are by desmearing treatment, whereby a micronized pattern of a photoresist filmcan be formed on the resin layer. Thus, interconnections, etc. can be formed over the resin layerat a narrow pitch with high reliability ensured.

The interposer includes a glass substratewith first through-electrodesburied in; a plurality of resin layerssupported by the glass substrate; thin film capacitorsburied between a first resin layerof the plural resin layers and a second resin layerof the plural resin layers and including the first capacitor electrodes, the second capacitor electrodesopposed to the first capacitor electrodes, and a dielectric thin filmof a relative dielectric constant of 200 or above formed between the first capacitor electrodeand the second capacitor electrode, and the second through-electrodespenetrating the plural resin layers, electrically connected to the first through-electrodeand electrically connected to the first capacitor electrodeor the second capacitor electrode

Interposer and method for manufacturing the same

A substrate support () having a flat supporting surface () is prepared, and a semiconductor substrate () is fixed to the substrate supporting surface () by attaching a wiring forming surface () to the supporting surface () by suction, for example, by vacuum suction. On this occasion, the wiring forming surface () is forcibly flattened by being attached to the supporting surface () by suction, and therefore the wiring forming surface () becomes a reference plane for planarization of a back surface (). In this state, planarization processing is performed by mechanically grinding the back surface () to grind away projecting portions () of the back surface (). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.

Semiconductor device, wiring substrate forming method, and substrate processing apparatus

A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode. The method further includes cutting an upper part of the first partial electrode and an upper part of the first resin layer with a cutting tool; forming on one primary surface of a second substrate a second resin layer as semi-cured, and a second partial electrode to be a part of the through-electrode, buried in the second resin layer and disposed in alignment with the first partial electrode; cutting an upper part of the second partial electrode and an upper part of the second resin layer with a cutting tool; making thermal processing with the first resin layer and the second resin layer in close contact with each other to adhere the first resin and the second resin layer to each other while jointing the first and second partial electrodes to each other; removing the first substrate; forming on said one primary surface of the second substrate a third resin layer, covering the thin-film capacitor, burying a third partial electrode to be a part of the through-electrode in the third resin layer, supporting the third resin layer by a supporting substrate; and removing the second substrate.

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Kawasaki, Japan

Kanae Nakagawa