Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Global Storage Technologies Netherlands B.v.

Hgst Netherlands, B.v.

Renesas Electronics Corportion

Nippon Tokushu Kent Co., Ltd.

Kan Yasui

Digh Hisamoto

Daisuke Okada

Tetsuya Ishimaru

Shinichiro Kimura

Toshihiro Tanaka

Akira Kato

Yasushi Ishii

Toshikazu Matsui

Souichi Katagiri

Tsutomu Okazaki

Kyoya Nitta

Yoshio Kawamura

Shigeo Moriyama

Nozomu Matsuzaki

Yasuhiro Shimamoto

Ui Yamaguchi

Sadayuki Nishimura

Toshiyuki Mine

Masahiko Sato

Nobuo Yoshida

Soichi Katagiri

Masayuki Nagasawa

Kenichi Akita

Masato Shiimoto

Takashi Yamaki

Tsuyoshi Arigane

Ryousei Kawai

Katsuhiko Yamaguchi

Keisuke Kuwahara

Shin-ichiro Kimura

Kazuhiro Suzuki

Natsuki Yokoyama

Yutaka Shinagawa

Yoshio Homma

Seiichi Kondo

Shin'ichiro Kimura

Yoshihiro Ishida

Takashi Kugaya

Yasufumi Morimoto

Shigeo Ootsuki

Daiske Okada

Ryosei Kawai

Harukazu Miyamoto

Katsuro Watanabe

Hiroyuki Hoshiya

Masukazu Igarashi

Kunio Harada

Yasushi Goto

Minoru Honda

Takashi Hirao

Koichi Toba

Hiroyuki Katada

Hiroyuki Yoshimoto

Kyoko Kojima

Hiroyuki Takazawa

Takeshi Nakagawa

Norihiro Okawa

Yasunobu Aoki

Takafumi Taniguchi

Satoshi Osabe

Yasafumi Morimoto

Masahiro Kaise

A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Semiconductor device

In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer.

Semiconductor device and power conversion device using same

In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field resistant sealing material corresponding to a reduced termination region having a high field intensity, and to improve accuracy and shorten time of manufacturing steps, this semiconductor device is configured as follows. At least a part of a cross-section of a high field resistant sealing material formed close to a termination region at the periphery of a semiconductor chip has a perpendicular shape at a chip outer peripheral end portion, said shape having, on the chip inner end side, a film thickness that is reduced toward the inner side. In a semiconductor device manufacturing method for providing such semiconductor device, the high field resistant sealing material is formed in a semiconductor wafer state, then, heat treatment is performed, and after dicing is performed, a chip is mounted.

Semiconductor device, method for manufacturing same, and semiconductor module

A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Fabrication method and structure of semiconductor non-volatile memory device

A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.

Nonvolatile semiconductor device and method of manufacturing the same

Semiconductor non-volatile memory device

Semiconductor device with gate electrodes

A microwave-assisted magnetic recording system configured to perform magnetic recording with high density, including a high-frequency magnetic field generation element whose width is narrower than a track width of a main pole. A magnetic field vector from the main pole is perpendicularly incident on a film surface of the high-frequency magnetic field generating unit, by a shield material arranged to have a high magnetic permeability so that the main pole magnetic field is corrected and induced, and a hard bias layer to which a desired static magnetic field is added. Areas having high magnetic field gradients overlap each other by performing an offset of the high-frequency magnetic field generating unit of the magnetic head from the central line of the main pole.

Energy-assisted magnetic recording head and magnetic recording device

A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate

Growing community of inventors

Kodaira, Japan

Kan Yasui