Renesas Electronics Corporation

Other

Renesas Technology Corp.

Kan Takeuchi

Kazumasa Yanagisawa

Hideo Aoki

Eiichi Murakami

Takayuki Oshima

Hizuru Yamaguchi

Kazuyuki Tsunokuni

Masaki Shimada

Takako Funakoshi

Kousuke Okuyama

Shinya Konishi

Fumio Tsuchiya

Toshihiro Tanaka

Yutaka Shinagawa

Daisuke Oshida

Masamichi Fujito

Takashi Yamaki

Takeshi Okagaki

Mitsuhiko Igarashi

Yoshio Takazawa

Naoya Ota

Mitsuru Hiraki

Makoto Ogasawara

Mitsuru Hirakii

A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.

Semiconductor device, electronic device and electronic system

An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.

Semiconductor device and semiconductor system

The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.

Semiconductor device and analysis system

In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.

Semiconductor device

There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.

An object of the invention is to provide a semiconductor apparatus capable of achieving conditions that are stricter than the conditions in which the stable operation is guaranteed, without increasing the circuit size. A semiconductor apparatus () includes a semiconductor circuit (); a voltage generator () that selects one of at least two types of voltages and applies a power supply voltage, the at least two types of voltages including a normal voltage at which the semiconductor circuit () normally operates and a low voltage which is lower than the normal voltage; and a clock generator () that supplies the semiconductor circuit () with a clock signal having a constant frequency regardless of the power supply voltage.

Semiconductor apparatus and system

In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.

In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 &#x3bc;m and is smaller than about 1.44 &#x3bc;m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 &#x3bc;m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Method of manufacturing a semiconductor integrated circuit device

A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 &#x3bc;m and is smaller than about 1.44 &#x3bc;m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 &#x3bc;m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Semiconductor integrated circuit device

A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

Growing community of inventors

Tokyo, Japan

Kan Takeuchi