Compaq Computer Corporation, Inc.

Kamran Khederzadeh

William C Hallowell

Todd J Deschepper

Russ Wunderlich

Fu Chan

A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management logic includes control logic, a stop clock register, an alternate stop clock register, and a wakeup event register. The operating system initiates a transition to a lower power mode of operation by issuing an IDLE call to the BIOS which responds by configuring a modulation value of 15 into the alternate stop clock register. With a modulation value of 15, the SLEEPREQ signal is continuously asserted disabling the CPU's internal clock. When a subsequent wakeup event occur, an enable bit in the alternate stop clock register is cleared, disabling modulation and deasserting SLEEPREQ. In response to the wakeup event, the amount of SLEEPEQ modulation is changed. Preferably the modulation value is changed to 14 so that SLEEPREQ is asserted for 14 out of every 15 cycles of a 32 KHz clock. The wakeup event register is configured to disable the system timer from being again causing a wakeup event. If a subsequent wakeup event is then detected, either the enable bit in the alternate stop clock register is cleared to disable SLEEPREQ modulation or the modulation value is programmed to a value of 0. If the enable bit is cleared, SLEEPREQ modulation is determined by the modulation value in a secondary stop clock register.

Smart battery power management in a computer system

A computer system in which various system peripherals are automatically re-initialized after being hot-swapped. The reinitialization includes accommodation of any required master/slave relationships between the peripherals.

Growing community of inventors

Houston, TX, United States of America

Kamran Khederzadeh