Canadian Patents & Development Ltd.

Canadian Patents and Development Limited/societe Canadienne Des Brevets

Canadian Patents & Dev. Limited

Kamilo Feher

Shuzo Kato

Jongsoo Seo

A signal processor for providing a continuous raised cosine output signal having no jitter or intersymbol-interference and with controllable main and side lobes. An NRZ input signal is converted to a double interval raised cosine pulse signal having an amplitude normalized to 1.0. Another single interval raised cosine pulse signal having a peak amplitude (A-1) is superposed with the former raised cosine pulse to provide the output signal.

Superposed quadrature modulated baseband signal processor

A cross-correlated baseband signal processor for providing in-phase and quadrature phase shifted NRZ signals from an input signal, apparatus for cross-correlating the in-phase and quadrature shifted signals, and apparatus for generating in-phase and quadrature shifted intersymbol-interference and jitter free (IJF) modulated output signals having amplitudes such that the vector sum of the output signals is approximately the same at virtually all phase angles of each bit period. The resultant cross-correlated bandlimited PSK signal (XPSK) has an almost constant envelope and thus it can be passed through a saturated amplifier without AM/PM and AM/AM degradation and without the need for post-amplification filtering, as there is no spectral restoration (regrowth).

Correlated signal processor

The jitter determining apparatus uses only a jittery clock signal of period T.sub.b recovered from the received data signal to determine peak to peak jitter J.sub.pp and jitter distribution. The apparatus includes an AND gate having a pair of inputs. The inputs are coupled to a first signal which is the jittery clock signal delayed by a fixed amount nT.sub.b where n is preferably greater than 5, and to a second signal which is a jittery pulse signal generated from the jittery clock signal. The second signal is also controllably delayed by a factor greater than twice the jitter J.sub.pp. The AND gate produces output pulses when coincidence occurs between the two signals as the delay of the second signal is selectively varied. A counter counts the pulses for each selected delay position and thus provides the peak to peak time jitter J.sub.pp of the clock signal.

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Ottawa, Canada

Kamilo Feher