Sonics, Incorporated

Kamil Synek

Michael Jude Meyer

Wolf-Dietrich Weber

Chien-Chun Chou

Drew Eric Wingard

Jay S Tomlinson

Scott Carlton Evans

Nabil Masri

Thomas Wayne O'Connell

A method and apparatus for automatic configuration of multiple on-chip interconnects have been described. In one embodiment, the invention reduces the configuration time of several on-chip network features, and also ensures that these features are configured correctly to minimize errors in a design.

Method and apparatus for automatic configuration of multiple on-chip interconnects

Methods and apparatuses for optimizing distributed multiplexed bus interconnects are described. Parameters of components that make up a distributed multiplexed bus interconnect may be optimized, such as an amount of area on a chip occupied by the component, an amount of power consumed by the component, etc., while satisfying existing timing constraints between nodes of a distributed multiplexed bus interconnect.

Method and apparatus for optimizing distributed multiplexed bus interconnects

Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.

Composing on-chip interconnects with configurable interfaces

A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.

On-chip inter-network performance optimization using configurable performance parameters

A method and apparatus for optimizing distributed multiplexed bus interconnects are described. The multiplexed bus interconnect contains one or more multiplexers to route signals through the bus interconnect. An amount of signaling wiring present within a distributed multiplexed bus interconnect is optimized by eliminating individual signaling wires based upon whether an Intellectual Property core connected to the multiplexed bus interconnect transmits or receives signals from the distributed multiplexed bus interconnect.

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Sunnyvale, CA, United States of America

Kamil Synek