Intel Corporation

Kamil Garifullin

Stanislav Shwartsman

Lihu Rappoport

Zeev Sperber

Andrey Kluchnikov

Pavel I Kryukov

Hong Wang

Sreenivas Subramoney

Igor Yanover

Adi Yoaz

Jayesh Gaur

Jared Warner Stark, Iv

Franck Sala

Andrey Efimov

Boris A Babayan

George Leifman

Sergey Y Shishlov

Alex Gerber

Adarsh Chauhan

Jared W Stark

Sumeet Bandishte

Igor Burovenko

Anton Lechanka

Anton Lechenko

A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

Automatic predication of hard-to-predict convergent branches

A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.

Instruction and logic for sorting and retiring stores

A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

Instruction and logic for register based hardware memory renaming

A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.

Apparatus and method for efficient memory renaming prediction using virtual registers

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Moscow, Russia

Kamil Garifullin