Qualcomm Incorporated

Kamesh Medisetti

Animesh Datta

Michael J Brunolli

Ohsang Kwon

Seid Hadi Rasouli

Mickael Malabry

Christine Sung-An Hau-Riege

Sucheta Kumar Harish

Prathiba Balasubramanian

Nikolay Bomshtein

Ramaprasath Vilangudipitchai

Smeeta Heggond

Seung Hyuk Kang

Giby Samson

Paras Gupta

Samrat Sinharoy

Jay Madhukar Shah

Keyurkumar Karsanbhai Kansagra

Gudoor Reddy

Vijayalakshmi Ranganna

Anil Kumar Koduru

Jitu Khushalbhai Mistry

Arshath Sheeparamatti

A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.

Systems and methods for adaptive power multiplexing

A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

Layout construction for addressing electromigration

A cell on an IC includes a first set of Mlayer interconnects coupled to a first voltage, a second set of Mlayer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mlayer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mlayer interconnects is coupled to the CTM. The second set of Mlayer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mlayer and an Mlayer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

MIMCAP architecture

A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

A standard cell CMOS device includes a first power rail extending across the standard cell. The first power rail is connected to one of a first voltage or a second voltage less than the first voltage. The device further includes a second power rail extending across the standard cell. The second power rail is connected to an other one of the first voltage or the second voltage. The second power rail includes a metal x layer interconnect and a set of metal x&#x2212;1 layer interconnects connected to the metal x layer interconnect. The device further includes a set of CMOS transistor devices between the first and second power rails and powered by the first and second power rails. The device further includes an x&#x2212;1 layer interconnect extending under and orthogonal to the second power rail. The x&#x2212;1 layer interconnect is coupled to the set of CMOS transistor devices.

Adaptive standard cell architecture and layout techniques for low area digital SoC

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Bengaluru, India

Kamesh Medisetti