Intel Corporation

Agere Systems Inc.

Lsi Corporation

Lucent Technologies Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Alcatel-lucent USA Inc.

Maxlinear, Inc.

Agere Systems Guardian Corp.

Avago Technologies International Sales Pte. Limited

Kameran Azadet

Albert Molina

Samer Lutfi Hijazi

Daniel Gruber

Ramon Sanchez

Martin Clara

Joseph Williams

Erich Franz Haratsch

Joseph H Othmer

Meng-Lin Yu

Hundo Shin

Jian-Guo Chen

Christian Lindholm

Matteo Camponeschi

Marc Jan Georges Tiebout

Donald Raymond Laturell

Ross Wilson

Zoran Zivkovic

Peter Kiss

Said E Abdelli

James F MacDonald

Fuji Yang

Steven Pinault

Sunitha Kopparthi

Shilpa Talwar

Hosein Nikopour

Bryan K Casper

Ofir Degani

Wook Bong Lee

Ashoke Ravi

Michael Genossar

Claudio Da Silva

Stefano Pellerano

Debabani Choudhury

Rotem Banin

Sidharth Dalmia

Georgios Yorgos Palaskas

Duncan Kitchin

Igal Kushnir

Oner Orhan

Saku Lahti

Emanuel Cohen

Mikko S Komulainen

Gadi Shor

Eren Sasoglu

Jayprakash Thakur

Arnaud Lucres Amadjikpe

Menashe Soffer

Ana M Yepes

Kunal Datta

Omer Asaf

Moshe Teplitsky

Run Levinger

Chintan S Thakkar

Eshel Gordon

Erkan Alpman

Josef Hagn

Nebil Tanzi

Ron Pongratz

Tawfiq Musah

Baljit Singh

Peter Sagazio

Amit Freiman

Eyal Goldberger

Yossi Tsfati

Kaushik Dasgupta

Eran Gerson

Shmuel Ravid

Noam Kogan

Nir Weisman

Shuhei Yamada

Marian K Verhelst

Anandaroop Chakrabarti

Meir Gordon

Resti Montoya Moreno

Miroslav Baryakh

Naftali Landsberg

Ra'anan Sover

Mikko M Lampinen

Avi Tsarfati

Jose Luis Ceballos

Zhan Yu

Kannan Rajamani

David Andrew Inglis

Chengzhou Li

Fadi Saibi

Jeroen Leijten

Chunbing Guo

Gregory Chance

Franz Kuttner

Alexander G Dickinson

Edwin Thaller

Gregory W Chance

Brandon R Davis

Carl Murray

Patrick Torta

Davide Ponton

Leilei Song

James M Yoder

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.

Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture

Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

Processing pipeline with zero loop overhead

A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

System and method for calibrating a time-interleaved digital-to-analog converter

A system and method for multi-band digital pre-distortion (DPD) for a non-linear system. The system includes a DPD circuitry configured to perform multi-band DPD on a multi-band input signal to compensate for a non-linearity of a non-linear system. The multi-band input signal includes input signals of multiple frequency bands and the DPD circuitry is configured to perform DPD on an input signal of each frequency band per frequency band. The DPD circuitry is configured to perform the DPD using a combination of a look-up table (LUT) that evaluates a non-linear function and computation of terms of a non-linear polynomial of one or more variables representing the input signals of multiple frequency bands. Both the non-linear function and the non-linear polynomial are in a reduced dimension lower than a dimension of the multi-band input signal.

Method and system for multi-band digital pre-distortion using a canonical form with reduced dimension look-up table

An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.

System and method for calibrating an analog-to-digital converter using a rational sampling frequency calibration digital-to-analog converter

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

Digital pre-distortion (DPD) adaptation using a hybrid hardware accelerator and programmable array architecture

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

Hybrid hardware accelerator and programmable array architecture

A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.

Processing device, transmitter, base station, mobile device, method and computer program

A system and method for digital correction for a dynamically varying non-linear system. The system includes a correction circuitry including at least one look-up table (LUT). The correction circuitry is configured to receive an input signal and modify the input signal to be processed by the non-linear system using at least one LUT to correct non-linearity incurred by the non-linear system. The at least one LUT is addressed by a magnitude or power of the input signal and a dynamically varying parameter associated with the input signal. The dynamically varying parameter may be one of average signal power of the input signal, a differential of the average power of the input signal, a directional beam index, or temperature.

Method and system for digital correction for a dynamically varying non-linear system

A method and apparatus for cancelling local oscillator feedthrough (LOFT). A transmitter includes a first mixer configured to mix a transmit signal with a first local oscillator signal. An observation receiver receives a fraction of a power of the transmit signal as a feedback signal and processes the feedback signal. The observation receiver includes a second mixer configured to mix the feedback signal with a second local oscillator signal. A LOFT correction estimation circuitry is configured to determine a DC offset to cancel LOFT at the first mixer in the transmitter based on measurements on outputs of the second mixer. An LOFT correction circuitry is configured to add the DC offset to the transmit signal. The LOFT correction estimation circuitry may determine the DC offset based on several measurements obtained by varying the DC offset and a phase shift in the second local oscillator signal in the observation receiver.

Method and apparatus for measuring and cancelling local oscillator feedthrough using an observation receiver

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

Wireless communication technology, apparatuses, and methods

A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

Method and system for digital equalization of a linear or non-linear system

A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

Chip-to-chip interface of a multi-chip module (MCM)

A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

Semiconductor devices, transceiver, base station and mobile device

Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.

Vector processor supporting linear interpolation on multiple dimensions

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Morganville, NJ, United States of America

Kameran Azadet