Rambus Inc.

Genapsys, Inc.

Lattice Semiconductor Corporation

Kambiz Kaviani

Amir Amirkhany

Dinesh D Patil

Frederick Abbott Ware

Farrukh Aquil

Jason Chia-Jen Wei

Aliazam Abbasfar

Huy M Nguyen

Farshid Aryanfar

Mohammad Hekmat

John M Wilson

Lei Luo

Barry William Daly

John Cronan Eble, Iii

Tsu-Ju Chin

Jared L Zerbe

Kun-Yung Chang

Hesaam Esfandyarpour

Reza Navid

Kosar Baghbani Parizi

Hamid Reza Rategh

Brian Hing-Kit Tsang

Kashinath Ullhas Prabhu

Xudong Shi

Meysam R Barmi

Scott C Best

Carl William Werner

Yohan Usthavia Frans

Thomas J Giovannini

Abhijit Mukun Abhyankar

Vijay Gadde

Chaofeng Huang

Marko Aleksić

Wayne D Dettloff

Omid Rajaee

Todd W Bystrom

Ting Wu

Wendemagegnehu Beyene

Hamid Rategh

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Optimizing power in a memory device

Provided herein are devices and methods suitable for sequencing, amplifying, analyzing, and performing sample preparation procedures for nucleic acids and other biomolecules.

Systems and methods for biological analysis

An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry having a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one reflected beacon from the second electronic device. The reflected beacon is received if a position of the second electronic device lies within a range of directions of the beacon. The transceiver circuitry further includes an injection-locked oscillator having an input coupled to the antenna array to receive reflected beacons, and to lock to the reflected beacon when the reflected beacon has a frequency value within locking range of the oscillator. Processing circuitry coupled to the transceiver circuitry tracks the position of the second device based on the lock condition of the oscillator.

High-accuracy and low-power tracking system for mobile devices

Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.

Electronic circuits using coupled multi-inductors

A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Reference voltage generation and calibration for single-ended signaling

A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

Offset and decision feedback equalization calibration

A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Partial response decision feedback equalizer with selection circuitry having hold state

A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Data buffer with strobe-based primary interface and a strobe-less secondary interface

Growing community of inventors

Palo Alto, CA, United States of America

Kambiz Kaviani