Raytheon Company

Kamal Tabatabaie

John P Bettencourt

Jeffrey R LaRoche

Valery S Kaper

Paul J Duval

William J Davis

Robert B Hallock

Kevin Iliff McCarthy

William E Hoke

Thomas E Kazior

Eduardo M Chumbes

John Michael Bedinger

Michael A Moore

Kelly P Ip

Michael S Davis

Kevin Mccarthy

Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

Method for processing semiconductors using a combination of electron beam and optical lithography

A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer.

Silicon based opto-electric circuits

A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. In effect, a sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact r&#xe9;sistance) all along the contact between the lower semiconductor layer and the electron donor layer.

Gallium nitride devices having low ohmic contact resistance

According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 10ohm-centimeter, and a defect density less than 0.5/centimeter.

Passivation layer for a circuit device and method of manufacture

A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer disposed between the first region and the second region. A fourth electrode is in electrical contact with the second portion of the seed layer.

Semiconductor structures having both elemental and compound semiconductor devices on a common substrate

A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.

Electrical contacts for CMOS devices and III-V devices formed on a silicon substrate

A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.

Atomic layer deposition in the formation of gate structures for III-V semiconductor

A method for forming a transistor device having a field plate. The method includes forming a structure having a source, a drain, and a Tee gate. A photo-resist layer is formed on the structure with an opening therein only the one of two distal ends of the Tee gate. A metal is deposited over the photo-resist layer with portions of the metal being disposed on the photo-resist layer and with other portions of the metal passing through the opening onto the exposed portions of the dielectric layer and with distal end of the top of the Tee gate preventing such metal from being deposited onto portions of the dielectric layer disposed under it. The photo-resist layer is removed along with the portions of the metal deposited thereon while leaving portions of the metal from regions of the dielectric layer exposed by the opening to form the field gate.

Growing community of inventors

Sharon, MA, United States of America

Kamal Tabatabaie