Altera Corporation

Kamal Patel

Paul Leventis

Joshua David Fender

Navid Azizi

James G Schleicher, Ii

Michael V Wenzler

Mihail Iotov

Jiunn Wen Chan

Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.

Pessimism removal in the modeling of simultaneous switching noise

In an example embodiment, an EDA program receives input which includes a selection as to an FPGA die and its device package and a selection as to a structured ASIC die and its device package. If the I/O pins on the device package for the FPGA differ from the I/O pins on the device package for the structured ASIC, the EDA program determines a correspondence between the I/O pins on the two device packages (e.g., by identifying the location of the pads for I/O pins on the structured ASIC die and/or creating a virtual structured ASIC device package whose I/O pins are a superset of the I/O pins on the selected structured ASIC device package), which determination includes checking rules for resource assignments. The EDA program then stores the determined correspondence in a device database where the determined correspondence can be accessed by CAD algorithms.

Interactive tool for contemporaneous design of integrated circuits having different device packages

Pin placement legality is verified in real-time in a background to reduce a number of input/output assignment analysis runs during a physical design of a programmable logic device. Edited pin properties are checked quickly in the background against certain rules, and results displayed to a user usually before a new pin is edited. Available and legal positions are found and displayed for a selected pin to reduce errors.

Real-time background legality verification of pin placement

A logic design system is provided for designing programmable logic device integrated circuits with minimized simultaneous switching noise. The logic design system identifies input-output drivers that are associated with simultaneous switching noise groups by examining a netlist for a circuit design for a programmable logic device. Simultaneous switching noise is minimized by making adjustments to programmable operating parameters for the input-output drivers. The logic design system may make adjustments such as adjustments to programmable drive strengths, programmable slew rates, and programmable on-chip termination resistances. During place and route operations, the logic design system makes placement decisions that help to minimize simultaneous switching noise.

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Campbell, CA, United States of America

Kamal Patel