Micron Technology Incorporated

Lodestar Licensing Group LLC

Kamal M Karda

Haitao Liu

Durai Vishak Nirmal Ramaswamy

Karthik Sarpatwari

Chandra V Mouli

Gurtej S Sandhu

Deepak Chandra Pandey

Sanh D Tang

Scott E Sills

Litao Yang

Yunfei Gao

Srinivas Pulugurtha

Kirk D Prall

Ramanathan Gandhi

Richard Edward Fackenthal

Si-Woo Lee

Yi Fang Lee

Akira Goda

F Daniel Gealy

Ashonita A Chavan

Qian Tao

Jaydip Guha

Fatma Arzum Simsek-Ege

Albert Fayrushin

Wolfgang Mueller

Shyam Surthi

Suraj J Mathew

Guangyu Huang

Rajesh N Gupta

Duane R Mills

Eric S Carman

Hung-Ming Tsai

John A Smythe

Lifang Xu

Kevin J Torek

Richard J Hill

Robert B Kerr

Sangmin Hwang

Fawad Ahmed

Sameer Chhajed

Sourabh Dhir

Hong Li

Vassil N Antonov

Alessandro Calderoni

Terrence B McDaniel

Manuj Nahar

Lars P Heineck

Hung-Wei Liu

Jeffery B Hull

Michael Mutch

Christian Caillat

Sheng-Wei Yang

Yingda Dong

David H Wells

Mark Fischer

Stephen J Kramer

Sumeet C Pandey

Marko Milojevic

Gianpietro Carnevale

Aurelio Giancarlo Mauri

Kamal Kumar Muthukrishnan

Ankit Sharma

Mingtao Li

Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first, second, and third conductive structures, each having a length in a first direction, first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction, first conductive regions, and second conductive regions. Each of the first and second memory cells includes a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures, a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures. The first conductive regions are opposite the first and second semiconductor portions, respectively, of the first memory cell. Second conductive regions are opposite the first and second semiconductor portions, respectively, of the second memory cell.

Memory device having tiers of 2-transistor memory cells

Some embodiments include a ferroelectric transistor having a first electrode and a second electrode. The second electrode is offset from the first electrode by an active region. A transistor gate is along a portion of the active region. The active region includes a first source/drain region adjacent the first electrode, a second source/drain region adjacent the second electrode, and a body region between the first and second source/drain regions. The body region includes a gated channel region adjacent the transistor gate. The active region includes at least one barrier between the second electrode and the gated channel region which is permeable to electrons but not to holes. Ferroelectric material is between the transistor gate and the gated channel region.

Ferroelectric transistors and assemblies comprising ferroelectric transistors

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line, a second data line, a conductive line, and a memory cell coupled to the first and second data lines. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the first and second data lines, and charge storage structure electrically separated from the first region. The second transistor includes a second region electrically separated from the first region, the second region electrically coupled to the charge storage structure and the second data line. The conductive line is electrically separated from the first and second channel regions. Part of the conductive line is spanning across part of the first region of the first transistor and part of the second region of the second transistor.

Memory device having shared read/write data line for 2-transistor vertical memory cell

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.

Memory device having 2-transistor vertical memory cell and shared channel region

An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

Array of vertical transistors and method used in forming an array of vertical transistors

A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

Devices including channel materials and passivation materials

A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

String driver assemblies including two-dimensional materials, and related memory devices

Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.

NAND structures with polarized materials

Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

Memory device having 2-transistor memory cell and access line plate

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.

Apparatus and method including memory device having 2-transistor vertical memory cell

A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

Devices including heterogeneous channels, and related memory devices, electronic systems, and methods

Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies

Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

Memory device having 2-transistor vertical memory cell and separate read and write gates

Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material and the channel material includes a second, different material.

Semiconductor devices and hybrid transistors

Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.

Memory device having 2-transistor vertical memory cell and conductive shield structure

Growing community of inventors

Boise, ID, United States of America

Kamal M Karda