Intel Corporation

University of Texas System

Kamal J Koshy

Jaroslaw Sydir

Wajdi K Feghali

Gilbert M Wolrich

Bradley A Burres

Chen-Chi Kuo

Raghavan Sudhakar

Sudarshan Kumar

Alok Kumar Mathur

Prasad Modali

Jiann-Cherng James Lan

Veerendra Bhora

Eduard Lecha

Poras T Balsara

Gilbert M Woolrich

A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.

Method and apparatus for performing an authentication after cipher operation in a network processor

An adaptive baseband processing system having a scalable architecture to allow scaling to support adaptive transmission and receive, at different granularity, channel vs. subchannel, for different number of antennas and/or users, including their components, are described herein. In various embodiments, the components include an adaptive antenna signal (AAS) coupled to a front-end processor, a back-end processor, or combinations thereof.

Scalable system to adaptively transmit and receive including adaptive antenna signal and back-end processors

In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.

Unified multi-mode receiver detector

A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.

Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor

An adaptive baseband processing system having a scalable architecture to allow scaling to support adaptive transmission and receive, at different granularity, channel vs. subchannel, for different number of antennas and/or users, including their components, are described herein. In various embodiments, the components include a front-end processor, an AAS processor and a back-end processor.

Embodiments of encoding input data into parity data in mechanisms are described generally herein. Other embodiments may be described and claimed.

Efficient CTC encoders and methods

An arrangement is provided for performing RC4 ciphering. The arrangement includes apparatuses and methods that pipeline generation of a key stream based on a byte state array, called the S-box, which is initially generated from a secret key shared by a receiver and a transmitter in a network system. The S-box is stored in a storage device which may be a register file with two read ports and one write port. A cache is used to store a number of bytes read from the S-box storage device.

Apparatus and method for performing RC4 ciphering

An arrangement is provided for performing MD5 digesting. The arrangement includes apparatuses and methods that pipeline the MD5 digesting process to produce a 128 bit digest for an input message of any arbitrary length.

Apparatus and method for performing MD5 digesting

An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be arranged to pipeline the process of performing iterations of multiple basic operations and other operations required to complete a Montgomery multiplication both horizontally and vertically. An MME may also be arranged to interleave processes of performing two Montgomery multiplications.

Method and apparatus for performing Montgomery multiplications

A data processing device includes a crypto unit having an alignment buffer for providing data to transmit buffer elements of a media switch fabric in multiples of a predetermined number of bytes. Ciphered data for a packet can be split over first and second transmit buffer elements so as to reduce the amount of software intervention.

Method and apparatus for aligning ciphered data

An arrangement is provided for performing the KASUMI ciphering process. The arrangement includes apparatuses and methods that parallelize computations of two FI functions in KASUMI rounds within one clock cycle and computes two consecutive FL functions in the KASUMI rounds within one clock cycle.

Growing community of inventors

Milpitas, CA, United States of America

Kamal J Koshy