International Business Machines Corporation

Globalfoundries Inc.

Kam-Leung Lee

Jeng-Bang Yau

Jack Oon Chu

Ahmet Serkan Ozcan

John Bruley

Paul Michael Solomon

Pouya Hashemi

Christian Lavoie

Kangguo Cheng

Alexander Reznicek

Keith E Fogel

Tak H Ning

Vijay Narayanan

Cyril Cabral, Jr

Haizhou Yin

Katherine Lynn Saenger

Martin Michael Frank

Chun-Yung Sung

Ronnen Andrew Roy

Nathaniel C Berliner

Tenko Yamashita

Huilong Zhu

Veeraraghavan S Basker

Stephen W Bedell

Oleg Gluschenkov

Dureseti Chidambarrao

Kevin K Chan

Hemanth Jagannathan

Son Van Nguyen

Jeffrey Bowman Johnson

Eduard Albert Cartier

Deborah A Neumayer

Qiqing Christine Ouyang

Emre Alptekin

John Albrecht Ott

Johnathan E Faltermeier

Michael John Hargrove

Jean Fompeyrine

Hyun-Jin Cho

Anthony Gene Domenicucci

Stefan Abel

Anda C Mocuta

Paul Andrew Ronsheim

Scott W Crowder

Hung Y Ng

Marinus J P Hopstaken

Liang-Kai Han

Mohammad Hasanuzzaman

Kai Chen

Silke H Christianson

A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

A method for converting a dielectric material including a type IV transition metal into a crystalline material that includes forming a predominantly non-crystalline dielectric material including the type IV transition metal on a supporting substrate as a component of an electrical device having a scale of microscale or less; and converting the predominantly non-crystalline dielectric material including the type IV transition metal to a crystalline crystal structure by exposure to energy for durations of less than 100 milliseconds and, in some instances, less than 10 microseconds. The resultant material is fully or partially crystallized and contains a metastable ferroelectric phase such as the polar orthorhombic phase of space group Pca2or Pmn2. During the conversion to the crystalline crystal structure, adjacently positioned components of the electrical devices are not damaged.

Fast recrystallization of hafnium or zirconium based oxides in insulator-metal structures

A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400&#xb0; C. or less.

Disposable laser/flash anneal absorber for embedded neuromorphic memory device fabrication

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shallow, abrupt and highly activated tin (Sn) extension implant junction. The method includes forming a semiconductor fin on a substrate. A gate is formed over a channel region of the semiconductor fin. A Sn extension implant junction is formed on a surface of the semiconductor fin in the channel region.

Shallow, abrupt and highly activated tin extension implant junction

A method of controlling formation of junctions in a lateral bipolar junction transistor comprises: providing a starting substrate comprising a bulk silicon material as a handle substrate, a buried oxide layer on the handle substrate, and an intrinsic base semiconductor layer of germanium on the buried oxide layer; forming an extrinsic base layer on the intrinsic base semiconductor layer; etching at least a portion of the base layer; disposing a sidewall spacer on a side of the base layer; disposing a faceted germanium layer adjacent the sidewall spacer; recessing the faceted germanium layer and the intrinsic base semiconductor layer below the sidewall spacer; using a hot angle ion implantation technique to implant ions into a side of the intrinsic base semiconductor layer to form a junction edge/profile; annealing the implanted ions; and epitaxially growing a Si or SiGe layer on the germanium layer and the junction edge/profile.

Method of junction control for lateral bipolar junction transistor

Embodiments of the invention include a method for forming a FinFET device and the resulting structure. A semiconductor device including a substrate, a silicon-germanium fin formed on the substrate, a dummy gate formed on the fin, and a first set of spacers formed on the exposed sidewalls of the dummy gate is provided. Xenon is implanted into the exposed portions of the fin. A second set of spacers are formed on the exposed sidewalls of the first set of spacer. A dopant is implanted into the exposed portions of the fin. The semiconductor device is thermally annealed, such that the dopants diffuse into the adjacent portions of the fin. The dummy gate is replaced with a gate structure.

Silicon-germanium FinFET device with controlled junction

A semiconductor device fabrication process includes forming a fin upon a semiconductor substrate and forming a gate upon the semiconductor substrate and upon and orthogonal to the fin, forming a source drain contacts by growing epitaxy material over the fin, forming a trench between the epitaxy material and a gate to expose an upper surface portion of the fin, doping the exposed fin portion to form an extension region, and activating the extension region. The semiconductor device may include the fin, gate, gate spacers upon sidewalls of the gate, a source drain contact adjacent to the gate spacers surrounding the fin, and doped extension regions within the fin below the gate spacers.

FinFET extension regions

A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFET fins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.

Conformal doping for FinFET devices

A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300&#xb0; C. to about 950&#xb0; C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.

Raised silicide contact

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Putnam Valley, NY, United States of America

Kam-Leung Lee