Intel Corporation

Kam Leung

Val Gene Cook

Wing Hang Wong

Hong Jiang

Peter L Doyle

Yan Hou

Michael Mantor

Aditya Sreenivas

Brian D Rauchfuss

John A Carey

Sajjad A Zaidi

R Scott Hartog

A machine readable storage media containing executable program instructions which when executed cause a digital processing system to set a plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.

Multiple texture compositing

A machine readable storage media containing executable program instructions which when executed cause a digital processing system to seta plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.

In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate ('MAC') processes such as the DCT ('Discrete Cosine Transform') and/or IDCT (&#x201c;Inverse Discrete Cosine Transform&#x201d;) using a performance optimized method and associated hardware apparatus.

Performance optimized approach for efficient numerical computations

An algorithm and hardware structure is described for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a plurality of adders and multipliers are reconfigurable via a switching fabric to operate as a plurality of MAAC ( multiply-add-accumulator) kernels (described in detail below), when operating in a non-downsampling mode and a plurality of MAAC kernels and AMAAC (add-multiply-add-accumulator) kernals (described in detail below), when operating in a downsampling mode.

Performance optimized approach for efficient downsampling operations

A method and circuit are provided for color space conversion of Y (luminance) and UV (chrominance) components from a planar YUV 4:2:0 format to an interleaved, or packed YUV 4:2:2 format, and from an interleaved, or packed YUV 4:2:2 format to a planar YUV 4:2:0 format. The method for both conversions includes reading source data, interpolating the sampled YUV component values, and performing a pass to thereby write the converted YUV component values in three passes, one pass for all values of the respective YUV components.

Method and apparatus for implementing 4:2:0 to 4:2:2 and 4:2:2 to 4:2:0 color space conversion

A pipeline apparatus for processing 3D graphics data will be described. The pipeline apparatus includes a first request memory to fetch information corresponding to a texture operand. A second request memory fetches information responding to a color operand and Z operand. A control circuit coordinates data flow from the first request memory and the second request memory into a memory channel by preventing the number of requests from the first request memory from exceeding by a predetermined number, the number of requests from the second request memory. By properly coordinating the data flow, deadlock of a data fetching pipeline is avoided.

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El Dorado Hills, CA, United States of America

Kam Leung