Siliconix Incorporated

Vishay-Siliconix

Kam Hong Lui

Kyle Terrill

Kuo-In Chen

Deva N Pattanayak

Frederick Perry Giles

Mohamed N Darwish

Robert Xu

Christiana Yue

Sharon Shi

Yuming Bai

Ronald Wong

King Owyang

Qufei Chen

Reuven Katraro

Mohammed Kasem

Calvin Choi

Misha Lee

Karl Lichtenberger

David Chang

Ben Chan

Christina Yue

Robert Q Xu

A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Semiconductor device with trench-like feed-throughs

Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

Trench metal oxide semiconductor with recessed trench material and remote contacts

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an 'off' condition, the bias of the buried source electrode causes the 'drift' region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Method of fabricating super trench MOSFET including buried source electrode

Super trench MOSFET including buried source electrode

In a trench-gated MIS semiconductor device, a slug of undoped polysilicon is deposited at the bottom of the trench to protect the gate oxide in this area against the high electric fields that can occur in this area. The slug is formed over a thick oxide layer at the bottom of the trench. A process of fabricating the MOSFET includes the steps of growing a thick oxide layer on the sidewalls and bottom of the trench, depositing a polysilicon layer which remains undoped, etching the polysilicon layer to form the plug, etching the exposed portion of the thick oxide layer, growing a gate oxide layer and an oxide layer over the plug, and depositing and doping a polysilicon layer which serves as the gate electrode. In an alternative embodiment, the oxide layer overlying the plug is etched before the gate polysilicon is deposited such that the dopant introduced into the gate polysilicon migrates into the polysilicon plug. In this embodiment, the polysilicon plug is in electrical contact with the gate polysilicon layer and is separated from the drain by the thick oxide layer.

Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same

Super trench MOSFET including buried source electrode and method of fabricating the same

In accordance with the present invention, a trench MOSFET is formed by creating a trench in a semiconductor substrate. A portion of either a side wall of the trench or the bottom of the trench is implanted with an implant species. An insulating layer is then grown overlying the bottom and side wall of the trench. The implant species is selected such that the insulating layer grows more quickly on the bottom of the trench than on the side wall of the trench, resulting in a thicker insulating layer in the bottom of the trench than on the trench side walls.

Self-aligned differential oxidation in trenches by ion implantation

Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

Method for making trench MIS device with reduced gate-to-drain capacitance

The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the body and drain regions intersects the trench in the transition region. This structure allows for a greater margin of error in the placement of the PN junction during the manufacture of the device, since the intersection between the PN junction can be located anywhere in the transition region. The MIS device also has improved breakdown characteristics.

Trench MIS device with graduated gate oxide layer

Trench MIS device with reduced gate-to-drain capacitance

A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to 'lift off', creating a 'bird's beak' structure. This becomes a &#x201c;transition region&#x201d;, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.

Method of fabricating trench MIS device with graduated gate oxide layer

Trench MOSFETs including active corner regions and a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such MOSFETs. In an exemplary embodiment, the trench MOSFET includes a thick insulative layer centrally located at the bottom of the trench. A thin gate insulative layer lines the sidewall and a peripheral portion of the bottom surface of the trench. A gate fills the trench, adjacent to the gate insulative layer. The gate is adjacent to the sides and top of the thick insulative layer. The thick insulative layer separates the gate from the drain conductive region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications.

Trench MIS device with active trench corners and thick bottom oxide

A trench MOSFET is formed by creating a trench in a semiconductor substrate, then forming a barrier layer over a portion of the side wall of the trench. A thick insulating layer is deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer deposits in the bottom of the trench at a faster rate than the thick insulating layer deposits on the barrier layer. Embodiments of the present invention avoid stress and reliability problems associated with thermal growth of insulating layers, and avoid problems with control of the shape and thickness of the thick insulating layer encountered when a thick insulating layer is deposited, then etched to the proper shape and thickness.

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Santa Clara, CA, United States of America

Kam Hong Lui