Intel Corporation

International Business Machines Corporation

Kalyan Muthukumar

Daniel M Lavery

Arvind Mandhani

Ashish V Choubal

Ajaya V Durg

Arvind Raman

Sundar Ramani

Raghavendra S Hebbalalu

Samudyatha Chakki

Jean-Francois C Collard

Gautam B Doshi

Shankar Ramaswamy

Barbara Bluestein Simons

Vikas Mishra

Anand V Bodas

Dz Ching Ju

David A Helder

Youfeng Wu

Dattatraya Kulkarni

Gerolf F Hoflehner

Gautam Doshi

Dong-Yuan Chen

Chu-Cheow Lim

Rama Kishan V Malladi

Robyn A Sampson

Seshadri Harinarayanan

Mukesh Gangadhar

Techniques are provided for mobile platform based detection and prevention (or mitigation) of hearing loss. An example system may include a hearing loss indicator data generation circuit configured to measure hearing loss indicator data associated with use of the device by a user. The hearing loss indicator data may include ambient sound characteristics, user speech volume level and user volume setting of the device. The system may also include an audio context generation circuit configured to estimate context data associated with use of the device. The context data may be based on classification of audio input to the device and on the location of the device. The system may further include an interface circuit configured to collect the hearing loss indicator data and the context data over a selected time period and provide the collected data to a hearing loss analysis system at periodic intervals.

Mobile device based techniques for detection and prevention of hearing loss

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Selecting a low power state based on cache flush latency determination

A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions.

Energy optimization techniques in a computing system

Various embodiments of the present invention relate to methods and systems for optimizing an intermediate code in a compilation logic. The intermediate code is optimized by performing reassociation in software loops. The intermediate code includes at least one critical recurrence cycle. The performance of reassociation in software loops can reduce a critical recurrence cycle in them, which can speed up their execution. The subject method can include the determination of one or more critical recurrence cycles in a software loop. The method can also include the determination of at least one edge in a critical recurrence cycle, with respect to which reassociation can be performed, if one or more pre-determined criteria are met. The method can further include performing reassociation of a dependee and a dependent of an edge. In an embodiment, when one or more pre-determined criteria are met, the logic of the software loop is maintained after performing reassociation of the dependee and the dependent of the edge. Consequently, the number of cycles in a critical recurrence cycle of the software loop is reduced. The execution time of the software loop is also decreased.

Method and system for performing reassociation in software loops

A method and system for optimizing the execution of a software loop is provided. The method involves the determination of an edge in a critical recurrence cycle in the software loop. The edge is a dependency link between two instructions and contains a dependee and a dependent. The dependee is an instruction that produces a result, and the dependent is an instruction that uses the result. The method further involves performing predicate promotion of at least one of the dependee and the dependent if one or more pre-determined conditions are met.

Method for predicate promotion in a software loop

Disclosed are embodiments of a compiler, methods, and system for resource-aware scheduling of instructions. A list scheduling approach is augmented to take into account resource constraints when determining priority for scheduling of instructions. Other embodiments are also described and claimed.

Resource-aware scheduling for compilers

An efficient method for software-pipelining (SWP) of loops to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer. In one example embodiment, this is accomplished by spilling and filling multiple computed values, in a register, that are live across multiple stages in a software-pipelined loop, using multiple rotating stack memory locations to reduce compiler-time of SWP, and complexity of the implemented SWP.

System, method, and apparatus for spilling and filling rotating registers in software-pipelined loops

A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the appropriate sub-location of a proxy storage location. The packed data is then written with a single instruction from the proxy storage location into contiguous memory locations.

Data repacking for memory accesses

A method that uses software-pipelining to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer, including sparse arrays/matrices. In one example embodiment, this is accomplished by transforming sparse array matrix source code and software-pipelining the transformed source code to reduce recurrence initiation interval, decrease run time, and enhance performance.

System and method for software-pipelining of loops with sparse matrix routines

The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined loop is initialized with a speculative instruction deactivated. At least one initiation interval of the software-pipelined loop is executed, and the speculative instruction is activated. Subsequent initiation intervals of the software-pipelined loop are then executed.

Mechanism to avoid explicit prologs in software pipelined do-while loops

Code restructuring or reordering based on profiling information and memory hierarchy is provided by constructing a Program Execution Graph (PEG) corresponding to a level of the memory hierarchy, partitioning this PEG to reduce estimated memory overhead costs below an upper bound, and constructing a PEG for a next level of the memory hierarchy from the partitioned PEG. The PEG is constructed from control flow and frequency information from a profile of the program to be restructured. The PEG is a weighted undirected graph comprising nodes representing basic blocks and edges representing transfer of control between pairs of basic blocks. The weight of a node is the size of the basic block it represents and the weight of an edge is the frequency of transition between the pair of basic blocs it connects.

Method of, system for, and computer program product for providing efficient utilization of memory hierarchy through code restructuring

A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.

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Bengaluru, India

Kalyan Muthukumar