Texas Instruments Corporation

Kalyan Chakravarthy Cherukuri

Stephanie Watts Butler

Kenneth Michael Butler

Venkataramanan Kalyanaraman

Hubert Joseph Payne

William J Vigrass

Yazdi Dinshaw Contractor

Richard Allen Faust

Alok Kumar

Thomas Edward Lillibridge

Rajkumar Jayaraman

Fenish Padinjaroot Prakasan

Praveen Krishnamurthy

Srinivas Raghavan

Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

Visual identification of semiconductor dies

Circuits and methods for controlling electrical coupling by a load switch are disclosed. In an embodiment, the load switch includes a pass element, level-shift circuit and low-resistance active path. The pass element is configured to be coupled to a power supply and a load, and is configured to electrically couple the power supply with the load during ON-state and electrically decouple the power supply from the load during OFF-state. The level-shift circuit includes a first transistor and pull-up resistor and is configured to generate a level-shifted signal in response to an enable signal, and enable the ON-state and the OFF-state of the pass element based on first and second voltages of the level-shifted signal. The low-resistance active path is coupled in parallel with the pull-up resistor for shunting the pull-up resistor in the OFF-state by providing a path for a leakage current of the first transistor in the OFF-state.

Load switch for controlling electrical coupling between power supply and load

A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.

Method of fabricating metal-bearing integrated circuit structures having low defect density

A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed space between each supporting chip and a next successive vertically stacked chip is described. The device is fabricated by patterning islands of aluminum atop the passivation layer of each supporting chip simultaneously with processing to form bond pad caps. The fabrication process requires no additional cost, and has the advantage of providing standoffs for a plurality of chips by processing in wafer form, thereby avoiding additional assembly costs. Further, the standoffs provide improved thermal dissipation for the device and a uniform, stable bonding surface for wire bonding each of the chips to the substrate.

Vertically stacked semiconductor device

Growing community of inventors

Allen, TX, United States of America

Kalyan Chakravarthy Cherukuri