Lsi Logic Corporation

Lsi Corporation

Kalvin E Williams

Christopher M Giles

Simon Bewick

Christopher J Lane

John S Holcroft

David Neil Pether

Gregor J Martin

A circuit generally comprising a first memory, a processor and a logic block is disclosed. The first memory may store (i) a write instruction to store a non-highest security value of at least three security values in a register and (ii) a jump instruction to a second memory. The processor may have a pipeline and may be configured to (i) bootstrap to the first memory while the register stores a highest security value of the security values and (ii) execute the jump instruction following the write instruction. The logic block may be configured to (i) detect the write instruction in an execution stage of the pipeline and (ii) store the non-highest security value in the register in response to detecting the write instruction in a write back stage of the pipeline.

Precise exit logic for removal of security overlay of instruction space

A circuit generally comprising a plurality of master modules and a supervisor module is disclosed. The supervisor module may be configured to (i) detect a target address and a particular master module of the master modules initiating a transaction on a bus, (ii) identify a predetermined authorization in response to the particular master module, the target address and a current security mode of at least three security modes and (iii) subvert the transaction in response to the predetermined authorization restricting the transaction.

Security supervisor governing allowed transactions on a system bus

A circuit generally comprising a logic module and a security module is disclosed. The logic module may be configured to set a plurality of values to a plurality of predetermined values respectively while in a scan mode. The security module may be configured to (i) disable a scan capability of the values while in a non-lowest security mode of at least three security modes and (ii) enabling the scan capability while in a lowest security mode of the security modes.

Scan and boundary scan disable mechanism on secure device

The invention may relate to a digital frequency adjuster for adjusting a first frequency of a first signal. The digital frequency adjuster may comprise a first digital delay line and a first control circuit. The first digital delay line may comprise a plurality of taps. The first digital delay line may be configured to (i) receive the first signal and (ii) generate a second signal. The first control circuit may be configured to control dynamic assertion of respective ones of the taps at a rate such that the second signal has a second frequency different from the first frequency of the first signal.

Frequency controller

A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.

Debug port disable mechanism

An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of processors and a message circuit. The message circuit may be configured to pass messages between the processors.

Method for multiprocessor communication within a shared memory architecture

An apparatus for receiving and processing an electrical signal in the form of a pulse train comprising a plurality of pulses. The apparatus generally comprises a processor, a memory and a timer. The timer may be configured to generate a respective value representative of the positions of each leading and trailing edge of each pulse in the pulse train. The memory may be configured to receive the value and write the value. The timer may be configured to generate an interrupt signal following receipt of the trailing edge of the last pulse in the pulse train and apply the interrupt signal to the processor. The processor may read the values stored in the memory for decoding the pulse train in response to said interrupt signal.

Cyclic buffer for infrared

A circuit generally comprising a first memory, a second memory and a processor is disclosed. The first memory may store an instruction to read an updated security value of at least three security values. The second memory may store (i) the updated security value and (ii) information related to security of the circuit. The processor may be configured to (i) execute the instruction while a register stores a highest security value of the security values, (ii) copy the information from the second memory to a third memory in response to the update security value being greater than a current security value of the security values stored in the third memory and (iii) ignore the information in the second memory in response to the updated security value being no greater than the current security value.

Use of EEPROM for storage of security objects in secure systems

A circuit generally comprising a memory element and a controller. The memory element may define a semaphore allocatable to a resource. The controller may be configured to (i) present a granted status in response to a processor reading a first address while the semaphore has a free status, (ii) set the semaphore to a busy status in response to presenting the granted status, and (iii) present the busy status in response to the processor reading the first address while the semaphore has the busy status.

Hardware semaphores for a multi-processor system within a shared memory architecture

A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

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Thatcham, United Kingdom

Kalvin E Williams