International Business Machines Corporation

Globalfoundries Inc.

Kalpesh Hira

Bill N On

James M Rakes

Giang Chau Nguyen

Jeffrey D Harper

Ivan Matthew Milman

Neil A Panchal

Ronald Dwayne Martin

A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Automating system on a chip customized design integration, specification, and verification through a single, integrated service

A network-based appliance includes a mechanism to erase data on the appliance's local storage. The appliance's normal system reset operation is overridden to enable a local user to place the appliance into a safe mode during which remote erasure of the storage is permitted, provided that mode is entered within a first time period following initiation of a system reset. If the appliance is placed in the mode within the time period, it can then receive commands to wipe the local storage. Once the safe mode is entered by detecting one or more actions of a local user, preferably the appliance data itself is wiped by another person or entity that is remote from the device. Thus, physical (local) presence to the appliance is necessary to place the device in the safe mode, while non-physical (remote) presence with respect to the appliance enables actual wiping of the storage device.

Multi-factor secure appliance decommissioning

Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into two groups based on the random order with high and low logical states respectively assigned to the two groups. In a specific implementation the latch states are set using an HDL force command prior to applying the reset signal, and the force command is removed after applying the reset signal using an HDL release command. If the circuit description is a gate-level netlist, then logical states of gates within the storage elements are also set.

Random initialization of latches in an integrated circuit design for simulation

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Austin, TX, United States of America

Kalpesh Hira