Intel Corporation

Kalpesh Dhanvantrai Mehta

Wen-Shan Wang

Louis A Lippincott

Krishna Shetty

Eric C Samson

Suketu R Partiwala

Eric F Vannerson

Wen-Shan (Vincent) Wang

Mike Donlon

Tinku Acharya

Frank T Hady

Sailesh Bissessur

James Chapple

Shashikiran H Tadas

Seng Thien Yap

An apparatus includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.

Decoder architecture systems, apparatus and methods

An apparatus is described comprising: logic circuitry to take an absolute difference between: 1) less than all of the bits of an uncompressed video data value from a reference macro block and 2) less than all of the bits of an uncompressed video data value from a macro block worth of data within a search window. The apparatus further includes a register to store the reference macro block. The register is coupled to the logic circuitry. The apparatus further include a random access memory to store the search window. The random access memory is coupled to the logic circuitry.

Motion estimation sum of all differences (SAD) array having reduced semiconductor die area consumption

According to some embodiments, context information is accessed for a current image block being processed. The context information may be, for example, associated with a block neighboring the current block, and the accessing may be performed in accordance with an address. At least one of a plurality of modular indexes may then be adjusted, and a next address may be determined in accordance with the plurality of modular indexes.

Context buffer address determination using a plurality of modular indexes

Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

Calculating display mode values

In one embodiment, a method and apparatus for filtering input pixel data is configurable to perform a one-dimensional or two-dimensional filtering process. Further, in one embodiment, the two-dimensional filter can be configured to perform a separable or non-separable filter. The type of filter can be configured, along with the size of the filter and other parameters. During operation, a stage I filtering operation performs a portion of the filter, and temporarily stores the result in a storage element. If the filter is a one-dimensional filter, then the results are sent to be post-processed. If the filter is a two-dimensional filter, then a stage II filtering process is performed or the intermediate results are added together, based on whether the filter is separable or non-separable. These results are then post-processed.

Image filtering methods and apparatus

Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Management of access to data from memory

A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various embodiments, the structure includes a current thread identifier, and a thread array of thread entries describing the threads to be executed interleavingly. Further, in various embodiments, the processing block includes an execution sub-block and a thread management sub-block equipped to support at least a create thread, a thread execution termination, and a thread execution switching instruction.

Processing block with integrated light weight multi-threading support

A device including a variable length coding unit that includes an input unit connected to a stream switching unit, and an output unit connected to the stream switching unit. The input unit to encode at least two input streams simultaneously. The output unit to transmit output streams to an output interface connected to the output unit.

Method and apparatus for multi-threaded variable length coding

A method, apparatus,and system for performing motion estimation using a logarithmic search are described. One or more image signal processing engines including a plurality of processing elements are employed. The one or more image signal processing engines are mutually coupled by a register file switch, and the one or more image signal processing engines perform a block matching calculation that includes a sum of absolute differences. The plurality of processing elements is further mutually coupled such that, during the block matching calculation, parallel processing and pixel data sharing of reference block pixel locations is employed by the plurality of processing elements.

Method and system for performing motion estimation using logarithmic search

Various embodiments of the invention relate to communicating data between a number of processing elements (PEs) of a signal processor, using a plurality of communication registers (CCRs). For instance, a plurality of the CCRs can be shared by and mapped to the address space of each PE, where each CCR couples a first of the PEs to every other one of the PEs. Moreover, each CCR can include a data payload field and a data valid field to indicate a target PE to read the data in the data payload field. Thus, data can be written to a selected CCR by a PE and stored in the selected CCR to be read by at least one target PE.

Communication registers for processing elements

Disclosed a processes and an apparatus which relates to an improved technique for sharing a computer resource.

Apportioning a shared computer resource

According to some embodiments, it is determined if a register is ready to exchange data with a processing element.

Determining if a register is ready to exchange data with a processing element

An address generator is provided with an input to receive a base address for an array of storage locations, an offset generator to generate a number of offsets, and a combiner coupled to the input and the offset generator to combine the base address with the offsets to generate a number of access addresses for accessing the array of storage locations in accordance with a deterministic access pattern having at least one non-sequential access. In various embodiments, the address generator is included in each of a number of signal processing units, which in turn are included in a digital media processor.

Non-sequential access pattern based address generator

Embodiments relate to converting or compressing symbols or run, level pair of an input digital video or image data stream to variable length code (VLC) by looking the symbols or run, level pairs up in a table including a binary code, a length code, and a flip code and constructing the VLC therefrom. For instance, the binary code may identify a first non-zero portion of the VLC, the length may identify the length of the VLC, and the flip code may identify whether or not the first portion and a number of 0's appended to the first portion to form a VLC having the length given by the length code, must be inverted to create the VLC. Also, the table may include entries grouped according to symbol or run, level pair values, and an address offset determined by the symbol or run, level pair or the input may be used to access the binary, length, and flip code from the appropriate group.

Growing community of inventors

Chandler, AZ, United States of America

Kalpesh Dhanvantrai Mehta