Micron Technology Incorporated

Nan Ya Technology Corporation

Kallol Mazumder

Navya Sri Sreeram

Scott Eugene Smith

Debra M Bell

Myung-Ho Bae

Jongtae Kwak

Jason M Brown

Parthasarathy Gajapathy

Tyler J Gomm

John Frederic Schreck

Vijayakrishna J Vankayala

William Chad Waldrop

Eric Booth

William D O'Leary

Ryo Fujimaki

Ravi Kiran Kandikonda

Takayuki Miyamoto

Roger D Norwood

Jeffrey Edward Koelling

Byung Sick Moon

Derek R May

Donald M Morgan

Yasuo Satoh

Kazutaka Miyano

Noriaki Mochida

Yutaka Uemura

Ming-Bo Liu

Tsugio Takahashi

Harish V Gadamsetty

Kangjoo Lee

Methods, apparatuses, and systems related to an apparatus implementing a geardown mode in a parallel pipeline configuration. The apparatus can include mechanisms to manage signal timing across multiple data processing pipelines for different communication speeds. While operating in a geardown mode, the apparatus can capture a sync pulse in two or more data pipelines. The apparatus can identify the pipeline that first captured the sync pulse and suppress the operation of the other pipelines.

Apparatus operating in geardown mode

Methods, systems, and devices for techniques for performing write operations are described. A controller of a memory system may generate a first command to write first data to a first set of memory cells of a memory array of the memory system. The controller may transmit the first command to a first buffer of the memory system. The first buffer may receive the first command and may generate the first data based on second data from a first address of a register. The first buffer may transmit the first data to the first set of memory cells, via a first buffer, based on the first command.

Techniques for performing write operations

Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a read state circuit configured to control the schedule/timing associated with parallel pipelines, and (2) a timing control circuit configured to coordinate output of data from the parallel pipelines.

Apparatus including parallel pipelines and methods of manufacturing the same

An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.

Memory device clock swapping

A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. Additionally, the memory device includes a state machine configured to receive a command into a first partition of the state machine and to enable a data strobe (DQS) input buffer in response to the indication. The state machine is also configured to maintain the enablement of the DQS input buffer while the command traverses the state machine. Furthermore, the state machine is configured to disable the DQS input buffer after a set duration of time.

Synchronous input buffer control using a state machine

An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.

Low power clock injection during idle mode operations

A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.

Ghost command suppression in a half-frequency memory device

Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.

Methods of reducing clock domain crossing timing violations, and related devices and systems

A memory device includes a command interface configured to receive a command from a host device. The memory device also includes a command shifter configured to receive the command. The command shifter includes a plurality of stages coupled in series and configured to delay the command. The command shifter comprises selection circuitry configured to receive the command and to select an insertion stage of the plurality of stages for the command. The selection circuitry is configured to select the insertion stage as a location to insert the command. The selected insertion stage is selected to control a duration of delay in the command shifter. The selection of the insertion stage is based at least in part on a path delay between a clock and a data pin of the memory device.

QED shifter for a memory device

A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a merged command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types. The merged command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.

Merged command decoder for half-frequency circuits of a memory device

Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.

Apparatus including parallel pipeline control and methods of manufacturing the same

The systems and methods described herein involve a device that may receive a plurality of commands and generate a common command indicative of matching data signals between each of the plurality of commands. The device may include a first latch that receives a shifted flag and outputs a shifted command in response to a first enable signal. The device may include shifters, where a first shifter may receive the common command, and a last shifter may couple to the first latch. The last shifter may receive a shifter common command and may generate the first enable signal using the shifted common command.

Shared command shifter systems and methods

Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.

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Plano, TX, United States of America

Kallol Mazumder