Texas Instruments Corporation

Kalipatnam V Rao

Allan T Mitchell

Howard L Tigelaar

James L Paterson

Joel T Tomlin

Shaym G Garg

Monica A Beals

Richard L Guldi

Kueing-Long Chen

A method of forming a semiconductor device includes forming a moat stack outwardly from a substrate, the moat stack comprising a dielectric pad disposed outwardly from the substrate, a silicon buffer structure disposed outwardly from the dielectric pad, and a protective dielectric cap disposed outwardly from the silicon buffer structure. The method further comprises forming a protective sidewall structure outwardly from at least a sidewall of the silicon buffer structure, forming an isolation dielectric region adjacent to the moat stack, after formation of the isolation dielectric region, removing the protective dielectric cap, and forming a conductive gate comprising the silicon buffer structure.

Method of simultaneous fabrication of isolation and gate regions in a semiconductor device

A method for forming LOCOS isolation regions which includes the steps of forming a polysilicon buffer layer between the pad oxide layer and the nitride layer and forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation region has reduced oxide encroachment into the active moat region.

Sidewall-sealed poly-buffered LOCOS isolation

This is a semiconductor device, comprising: a semiconductor body having an isolation region separating at least two active device regions; pad oxide layers disposed on said active regions; polysilicon layers disposed on said pad oxide layers; silicon nitride layers disposed on said polysilicon layers; and a sidewall seal disposed all along the perimeter of the active device regions to seal said active device regions against oxygen diffusion. The resulting field oxide isolation region has reduced oxide encroachment into the active moat region.

A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.

Interlevel dielectric process

The disclosure relates to a method for reducing filament formation over the BN+ oxide in semiconductor devices wherein a sidewall oxide is formed on the side walls of the first polysilicon layer prior to subsequent formation of the intermediate insulating layer, formation of a second polysilicon layer and subsequent anisotropic etch to provide for removal of all polysilicon over the field oxide.

Method for reduction of filaments between electrodes

A process for obtaining extremely smooth interfaces of poly 1/inter-level dielectric film/poly 2 films. Essentially, the poly 1 layer is LPCVD-deposited in the amorphous phase and implant-doped, after which an appropriate dielectric film is deposited by LPCVD. Following this, the poly 1 is crystallized at a temperature of about 1000.degree. C., after which poly 2 is LPCVD-deposited and POCl.sub.3 -doped at 950.degree. C. The resulting poly 2/inter-level dielectric/poly 1 interfaces are extremely smooth on an atomic scale, even after other device fabrication thermal cycles, and are believed to resutl in superior leakage characteristics.

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Plano, TX, United States of America

Kalipatnam V Rao