Altera Corporation

Kalen Brunham

Joshua David Fender

Gordon Raymond Chiu

Mahesh A Iyer

Ryan Fung

Scott J Weber

Kevin Nealis

Yi Peng

Christine Lau

Gordan Raymond Chiu

Devices and methods for initializing one or more registers of a programmable integrated circuit (IC) to store an initial condition value are provided. A first bitstream that programs the region of the IC to supply the initial condition value to the one or more registers is first programmed on the IC. Then, once the registers are initialized with the initial condition value, a second bitstream is subsequently programmed to the region of the IC to supply values associated with a function of the design to the one or more registers.

Initial condition support for partial reconfiguration

Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and pass from registers in the partial reconfiguration partitions to the static partition, and to ensure that these registers are each in a defined state after the partial reconfiguration operation and a register reset operation are completed.

Partial reconfiguration debugging using hybrid models

A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration

An external memory interface includes an input/output (IO) logic unit operable to convert a rate of data from a first rate corresponding to a memory controller/schedule unit to a second rate corresponding to an external memory device. The external memory interface also includes a latency adjustment unit, operating in a timing domain of the memory controller/schedule unit, operable to add between 1 to [(second rate/first rate)&#x2212;1] cycles of latency of the second rate.

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Toronto, Canada

Kalen Brunham