Intel Corporation

Kaladhar Radhakrishnan

Krishna Bharath

William J Lambert

Dustin P Wood

Michael J Hill

Adel A Elsherbini

Beomseok Choi

Nicholas Holmberg

Kemal Aygun

Zhiguo Qian

Amruthavalli Pallavi Alur

Yikang Deng

Yongki Min

Huong T Do

Clive R Hendricks

Johanna M Swan

Shawna M Liff

Edward Allyn Burton

Jonathan P Douglas

Brent S Stone

Joel A Auernheimer

Reynaldo Alberto Olmedo

Leigh E Wojewoda

Venkat Anil K Magadala

Robert L Sankman

Donald S Gardner

Tanay Karnik

Fabrice Paillet

Gerhard Schrom

Peter Hazucha

Cengiz Ahmet Palanduz

Sriram Srinivasan

Dong Zhong

Amit Kumar Jain

Christopher Schaef

Alexander Slepoy

Sameer Shekhar

Srikrishnan Venkataraman

Sung Tae Moon

Timothe Litt

Trang T Nguyen

Kimberly Dawn Eilert

Hector A Aguirre Diaz

Larry Binder

Aleksandar Aleksov

Feras Eid

Stephen L Morein

Debendra Mallik

Henning Braunisch

Mathew J Manusharow

Sanka Ganesan

Mihir K Roy

Cheng Xu

Joshua Heppner

Larry E Mosley

Junnan Zhao

Hao-Han Hsu

Andrew James Brown

Dong-Ho Han

Sri Chaitra Jyotsna Chavali

Jaejin Lee

Ashay A Dani

Chung-Hao Chen

Chin Lee Kuan

Ying Wang

Sriram Dattaguru

Gregorio R Murtagian

Jung S Kang

David Bach

Anne Augustine

Malavarayan Sankarasubramanian

Siddharth Kulasekaran

Christopher C Jones

Wei Shen

Shamala A Chikamenahalli

Chris Jones

Dave Bach

Embodiments disclosed herein include microelectronic boards and electronic systems. In an embodiment, a microelectronic board comprises aboard substrate, where the board substrate has a first thickness between a first surface and a second surface opposite from the first surface. In an embodiment, a recess is formed into the first surface of the board substrate, where the recess comprises a third surface between the first surface and the second surface. In an embodiment, the board substrate has a second thickness between the third surface and the second surface. In an embodiment, the microelectronic board further comprises a voltage regulator (VR) module attached to the third surface.

Backside recess in motherboard with thermally conductive mold

Embodiments disclosed herein include electronic packages with embedded inductors. In an embodiment, an electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment, the electronic package further comprises an inductor embedded in the package substrate, where the inductor comprises: a trace with a first end and a second end. In an embodiment, a magnetic material surrounds the trace between the first end and the second end. In an embodiment, a first via is connected to the first end, and a second via is connected to the second end.

Planar magnetic radial inductors to enable VR disaggregation

An inductor can be formed in a coreless electronic substrate, such that the fabrication process does not result in the magnetic material used in the inductor leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming conductive vias with a lithographic process, rather than a standard laser process, in combination with panel planarization to prevent exposure of the magnetic material to the plating and/or etching solutions/chemistries.

Coreless electronic substrates having embedded inductors

A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

Packaging architecture for disaggregated integrated voltage regulators

In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

Conformal power delivery structure for direct chip attach architectures

In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures

Embodiments disclosed herein include two stage voltage regulators for electronic systems. In an embodiment, a voltage regulator comprises a switched capacitor voltage regulator (SCVR). In an embodiment, the SCVR receives a first voltage as an input and outputs a plurality of SCVR output voltages. In an embodiment, the voltage regulator further comprises a low-dropout (LDO) regulator. In an embodiment, the LDO regulator receives one or more of the plurality of SCVR output voltages as LDO input voltages, and where the LDO regulator outputs a second voltage.

Two stage multi-input multi-output regulator

Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

Multi-phase switching regulators with hybrid inductors and per phase frequency control

A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

Package-integrated multi-turn coil embedded in a package magnetic core

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

Microelectronic assemblies having an integrated voltage regulator chiplet

Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

Magnetic structures in integrated circuit package supports

Embodiments include an inductor, a method to form the inductor, and a semiconductor package. An inductor includes a plurality of plated-through-hole (PTH) vias in a substrate layer, and a plurality of magnetic interconnects with a plurality of openings in the substrate layer. The openings of the magnetic interconnects surround the PTH vias. The inductor also includes an insulating layer in the substrate layer, a first conductive layer over the PTH vias, magnetic interconnects, and insulating layer, and a second conductive layer below the PTH vias, magnetic interconnects, and insulating layer. The insulating layer surrounds the PTH vias and magnetic interconnects. The magnetic interconnects may have a thickness substantially equal to a thickness of the PTH vias. The magnetic interconnects may be shaped as hollow cylindrical magnetic cores with magnetic materials. The magnetic materials may include ferroelectric, conductive, or epoxy materials. The hollow cylindrical magnetic cores may be ferroelectric cores.

Coaxial magnetic inductors with pre-fabricated ferrite cores

A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

Integrated multi-die partitioned voltage regulator

The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

Package substrates with magnetic build-up layers

An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

Via-in-via structure for high density package integrated inductor

Growing community of inventors

Chandler, AZ, United States of America

Kaladhar Radhakrishnan