Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Kaizad R Mistry

Hamid Partovi

David Benjamin Krakauer

Jeffrey William Sleight

Steven W Butler

Lawrence Bair

William A McGee

An improved MOSFET transistor is disclosed having a high dielectric constant gate dielectric and a metal gate electrode. With such a procedure, the known problems with polysilicon gate electrodes on very thin gate oxide transistors are greatly improved, resulting in improved gate threshold voltage control and improved transistor electrical properties, without loss of the benefit of self aligned source and drain electrodes available with polysilicon gates. Dual metal gate electrodes are also disclosed and exhibit improved CMOS transistor function compared to polysilicon gates, resulting in better and more controlled transistor properties. Thus the metal Damascene gate process results in faster and more consistent MOS and CMOS transistors and improved IC fabrication.

Damascene process for MOSFET fabrication

A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown. This insures that the ESD clamp reaches its snapback voltage before the onset of junction breakdown in the operating circuits. The circuit is especially useful in integrated circuits where the gate oxide of a standard ESD clamp transistor is too thin to protect the operating logic from I/O signal voltages that are greater than the supply voltage used for the operating logic circuits.

Electro-static discharge protection device having a modulated control

A field effect transistor structure having: a first type conductivity semiconductor body disposed on an insulator and having formed in different regions thereof: (a) a source region; (b) a drain region, such source and drain regions being of a conductivity type opposite the conductivity type of the body; (c) a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions; and (d) a Schottky contact region providing a Schottky diode between the semiconductor body and one of the source and drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 V, between the semiconductor body and one of the source and drain regions. A method for forming a semiconductor structure, comprising the steps of: providing a semiconductor body over an electrical insulator; providing source and drain areas in the semiconductor body on either side of a gate channel; introducing dopant into un-masked portions of the source and drain areas to form source and drain regions in the semiconductor body, such mask blocking such dopant from passing into the masked portion of at least one of the source and drain areas and the contiguous portion of the semiconductor body; and forming a metal between the masked portion of the at least one of the source and drain regions and the contiguous portion of the semiconductor body. The metal forming step may be performed prior to, or subsequent to, the dopant introduction step.

Compact self-aligned body contact silicon-on-insulator transistors

A field effect transistor structure having a first type conductivity semiconductor body disposed on an insulator and having formed in different regions of the semiconductor, a source region and a drain region of the opposite type conductivity to the first type, a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions, and a Schottky diode contact region between the semiconductor body and one of the source or the drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 volts, between the semiconductor body and one of the source or the drain regions.

Compact self-aligned body contact silicon-on-insulator transistor

An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of series connected inverters powered by the signal pad voltage in an alternate embodiment. The inverter chain is coupled to the ESD clamp. The modulation circuit requires no reference supply voltage to operate. The ESD protection circuit shunts currents associated with ESD events away from ICs as well as clamping I/O pad voltages to acceptable levels during an ESD event.

Self-referencing modulation circuit for CMOS integrated circuit

A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs. The clamping performed by the invention reduces wearout and other deleterious effects of excess voltage.

Field effect transistor with integrated schottky diode clamp

An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors. A standard process for making CMOS integrated circuits having self-aligned silicided source/drain areas may be used, with the addition of only one non-critical masking step to block the siliciding of protection transistors.

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Brighton, MA, United States of America

Kaizad R Mistry