Altera Corporation

Kaiyu Ren

Adam J Wright

Peter Boyle

San Wong

Qi Chen

Binh Vo

John DiCosola

Laiq Chughtai

Wan-Pin Hung

Seng Yew Lim

Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

Functional failure analysis techniques for programmable integrated circuits

The present invention provides a bit error rate tester implemented in a programmable logic device. Any or all of the components of the bit error rate tester may be implemented through software by programming the programmable logic circuitry of the programmable logic device to implement the components of the bit error rate tester. The bit error tester may determine the bit error rate of any suitable interface either within the programmable logic device or external to the programmable logic device. In order to allow a user to interact with the bit error rate tester, user equipment, such as a personal computer, may be coupled to the bit error rate tester.

Bit error rate tester implemented in a programmable logic device

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San Jose, CA, United States of America

Kaiyu Ren