Kioxia Corporation

Toshiba Memory Corporation

Kaito Shirai

Hideto Takekida

Tatsuo Izumi

Takahisa Kanemura

Shigeo Kondo

Reiko Shamoto

Hanae Ishihara

Masaya Ichikawa

Takashi Sugihara

Satoshi Kotomari

A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.

Semiconductor memory device

A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.

Semiconductor device and method of manufacturing the same

According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.

A semiconductor chip includes a memory cell array and a wiring layer. The memory cell array includes a plurality of blocks arranged in a first direction along a surface of the semiconductor chip. The wiring layer includes a plurality of first pattern regions at different positions along the first direction, each first pattern region including a different pattern corresponding to one or more of the blocks. The first pattern regions can be used to identify portions of the semiconductor chip during analysis or the like.

Growing community of inventors

Yokkaichi, Japan

Kaito Shirai