Avago Technologies General IP (singapore) Pte. Ltd.

Lsi Corporation

Avago Technologies International Sales Pte. Limited

Kaitlyn T Nguyen

Shaohua Yang

Fan Zhang

Jun Xiao

Dan Liu

Qi Zuo

Ku Hong Jeong

Shu Li

Zongwang Li

Yang Han

Weijun Tan

Chung-Li Wang

Xuebin Wu

Kevin G Christian

Yoon Liong Liow

Yu Chin Fabian Lim

Xiao Dong Yan

Zuo Qi

Keklik Bayam Alptekin

The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.

System and method for despreader memory management

An apparatus for processing data includes a data detector configured to detect data values in data sectors to yield detected data, a data decoder configured to decode the detected data, wherein the data detector and the data decoder are configured to process the data sectors in a series of global iterations, a memory configured to store parity sector soft information, and a scheduler configured to control overlapping reprocessing of a failed sector in the data detector and the data decoder based on the parity sector soft information with processing of another data sector in the data detector and the data decoder.

Systems and methods for overlapping parity sectors

An apparatus for processing data includes a data processing circuit configured to process user data, wherein the data processing circuit comprises a number of sub-circuits, a number of clock gates each configured to control a clock signal to one of the sub-circuits, a gating control circuit configured to control the clock gates to apply the clock signal to each of the sub-circuits in staged fashion during a ramped power up operation, and a dummy data source configured to provide dummy data to the data processing circuit during the ramped power up operation of the data processing circuit.

Systems and methods for processing data with power ramp control

Systems and method relating generally to data processing, and more particularly to systems and methods for modifying symbols in a data set prior to re-processing.

Systems and methods for efficient targeted symbol flipping

Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for quality based scheduling processing of data sets. In some cases, a priority indication associated with a data set is modified based upon one or more factors. As an example, the priority indication may be modified based upon a number of times that a given data set processed through both a data detector circuit and a data decoder circuit.

Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for use of a detector output by a data decoder. As an example, a data processing system is discussed that includes a data detector circuit operable to provide a first detector output and a second detector output, and a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output. The combined detector output includes a unified data set element generated by combining an element of the first input with a corresponding element of the second input.

Systems and methods for data processing using global iteration result reuse

The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a converted CNU message having sub-circulants sized for RAM-based processing. The decoder further includes RAM configured to store sub-circulants of the converted CNU message at addressable memory blocks for parallel VNU processing.

System and method for check-node unit message processing

Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for re-processing data sets not successfully processed during standard processing.

Systems and methods for selective retry data retention processing

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing with soft guaranteed global processing iterations.

Growing community of inventors

San Jose, CA, United States of America

Kaitlyn T Nguyen