Texas Instruments Corporation

Kaiping Liu

Imran Khan

Zhiqiang (Jeff) Wu

Amitava Chatterjee

Jihong Chen

Richard Allen Faust

Amitabh Jain

Allan T Mitchell

Antonio Luis Pacheco Rotondaro

Shaoping Tang

John Paul Campbell

Haowen Bu

Jiong-Ping Lu

Manoj Mehrotra

Jau-Yuann Yang

Yuanning Chen

Song Zhao

Lance Stanford Robertson

Duofeng Yue

Sue E Crank

Donald S Miles

Majid Movahed Mansoorz

Hamseswari Renganathan

A method of fabricating ICs including thin film resistors (TFRs) depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry comprising a plurality of interconnected transistors. A TFR layer comprising chromium (Cr) is deposited on the dielectric liner layer. The TFR layer is plasma treated with atomic nitrogen and atomic hydrogen. A dielectric capping layer is deposited on the TFR layer after the plasma treating. A pattern is formed on the capping layer, and the TFR layer is etched to form at least one resistor that comprises the TFR layer.

Plasma treatment for thin film resistors on integrated circuits

An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Low cost demos transistor with improved CHC immunity

A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

High precision capacitor dielectric

An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Multiple depth vias in an integrated circuit

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.

Analog floating-gate capacitor with improved data retention in a silicided integrated circuit

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Low leakage capacitor for analog floating-gate integrated circuits

The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor

A complementary metal oxide semiconductor (CMOS) device has a substrate, a gate structuredisposed atop the substrate, and spacers, deposited on opposite sides of the gate structureto govern formation of deep source drain regions S, D in the substrate. Spacersare formed of an oxynitride (SiONC) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate, forming a gate structureover the substrate, depositing a first layeratop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiONC) layeratop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layeratop the oxynitride layer, and depositing a nitride layerB atop the second layer.

Using oxynitride spacer to reduce parasitic capacitance in CMOS devices

A process () for making integrated circuits with a gate, uses a doped precursor (N and/orP) on barrier material () on gate dielectric (). The process () involves totally consuming () the doped precursor (N and/orP) thereby driving dopants (N and/orP) from the doped precursor () into the barrier material (). An integrated circuit has a gate dielectric (), a doped metallic barrier material (N and/orP) on the gate dielectric (), and metal silicide () on the metallic barrier material (). Other integrated circuits, transistors, systems and processes of manufacture are disclosed.

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Plano, TX, United States of America

Kaiping Liu