Xilinx, Inc.

Winbond Electronics Corporation

Kaiman Chan

Shuxian Wu

Chun-Mai Liu

Jane W Sowards

Kung-Yen Su

An aspect of the invention relates to modeling a transistor in an integrated circuit design. Layout data for the integrated circuit design is obtained. A geometry relating the transistor to at least one well edge of at least one implant well is extracted from the layout data. An effective well proximity value for the transistor is calculated based on the at least one well edge using a complementary error function. The transistor is modeled using the effective well proximity value. In one embodiment, the effective well proximity value is added to a post-layout extracted netlist for the integrated circuit design. The integrated circuit design may be simulated using the post-layout extracted netlist. The effective well proximity value may be used to calculate a threshold voltage for the transistor during the step of simulating the integrated circuit.

Method and apparatus for modeling transistors in an integrated circuit design

A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n&plus; diffusion region and a source-side n&plus; diffusion region which are separated by a field oxide. The FOD further includes a p&plus; doped region that interfaces with the drain-side n&plus; diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p&plus; doped region. The FOD may additionally include one or more n&plus; regions at the respective boundaries of the drain-side and source-side n&plus; diffusion regions to provide improved junction curvature. In addition to the field oxide interposed between the drain-side and source-side n&plus; diffusion regions, field oxides can be added respectively at the drain and source ends to provide isolation from other devices within an integrated circuit.

Growing community of inventors

Fremont, CA, United States of America

Kaiman Chan