Massachusetts Institute of Technology

Kailiang Chen

Neil Adam Gershenfeld

David Allen Dalrymple

Charles G Sodini

Jonathan Leu

An ultrasonic imaging system is described in which a column-row-parallel architecture is provided at the circuit level of an ultrasonic transceiver. The ultrasonic imaging system can include a N&#xd7;M array of transducer elements and a plurality of transceiver circuits where each transceiver circuit is connected to a corresponding one transducer element of the N&#xd7;M array of transducer elements. A shared pulser gate driver and a shared VGA is provided for each row and column. Selection logic includes row select, column select, and per-element bit select. Through the column-row-parallel architecture, a variety of aperture configurations can be achieved.

Application specific integrated circuit with column-row-parallel architecture for ultrasonic imaging

A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.

Analog logic automata

A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.

Asynchronous logic automata

A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.

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Kailiang Chen