Synopsys, Inc.

Stmicroelectronics International N.v.

Stmicroelectronics (rousset) Sas

Kailash Kumar

Prateek Singh

Manoj Kumar

Akhil Thotli

Nicolas Demange

Ravinder Kumar

Rahul Gupta

Sriram Kumar Jayanthi

A dynamic gate control signal generator circuit includes a pad configured to produce an output voltage, a reference generator configured to receive a supply voltage (VDDIO) and produce, based on the supply voltage, a first reference voltage signal and a second reference voltage signal, and a pad tracker circuit coupled to the reference generator, the pad tracker circuit configured to receive the output voltage of the pad and limit a high voltage of the pad to the second reference voltage signal. The dynamic gate control signal generator circuit further includes a first clamper circuit coupled to the pad tracker, the first clamper circuit configured to receive an output voltage signal from the pad tracker circuit and generate, based on the output voltage signal, a dynamic gate control signal that toggles between the first reference voltage signal and the second reference voltage signal.

Dynamic gate control signal supply voltage generation in electronic circuits

An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.

Integrated circuit with output driver that compensates for supply voltage variations

An electric circuit and a method for filtering glitches are described. The electric circuit includes a filter, an inverter circuit, and a reset circuit. The inverter circuit is electrically coupled to an output of the filter. The reset circuit is electrically coupled to the output of the filter. The reset circuit pulls the output of the filter high when an input signal to the electric circuit and the output of the inverter circuit are both low, pulls the output of the filter low when the input signal to the electric circuit and the output of the inverter circuit are both high, and passes the output of the filter when (i) the input signal to the electric circuit is high and the output of the inverter circuit is low or (ii) the input signal to the electric circuit is low and the output of the inverter circuit is high.

Glitch filter with reset circuit

A circuit provides fail safe protection of an input/output (I/O) circuit of a chip. The I/O circuit comprises an I/O pad connected to one or more other chips via an I/O bus. The circuit comprise a supply and failsafe detector component. The supply and failsafe detector component generates an I/O supply output signal. The I/O supply output signal has a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high voltage value when the I/O supply voltage of the chip is above the medium voltage level. The medium voltage is above a threshold voltage of the transistor of the I/O circuit and below the high voltage value. The circuit uses the I/O supply output signal to provide a reference voltage as input to the transistor of the I/O circuit.

Fail-safe protection architecture for high voltage tolerant input/output circuit

An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.

Schmitt trigger with current assistance circuit

A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.

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Hazaribagh, India

Kailash Kumar